18 Dec, 2020
2 commits
-
* pxp/next: (8 commits)
LF-1596 dma: pxp: add checking for out against NULL
LF-1595 dma: pxp: fix the typo for possible_inputs_s1 checking
LF-1594 dma: pxp: fix out-of-bounds access
LF-1162-19 media: mxc: pxp_v4l2: change to use VFL_TYPE_VIDEO
LF-105-1 dmaengine: pxp: fix build warning of fall through
... -
* origin/dma/edma: (31 commits)
MLK-24825-2: dmaengine: fsl-edma: checking ACTIVE bit for channel stop
MLK-24825-1: dmaengine: fsl-edma-v3: checking ACTIVE bit for channel stop
MLK-24292: dmaengine: fsl-edma-v3: correct power domain attach checking
LF-631-2 dt-bindings: fsl-edma: Document support for S32V234
LF-631-4 dmaengine: fsl-edma: Add support for S32V234
...
14 Dec, 2020
3 commits
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Porting pxp dma drivers v2 and v3 from imx_4.19.y
Signed-off-by: Robby Cai
-
Add edma-v3 driver on i.mx8qm.
Signed-off-by: Robin Gong
(cherry picked from commit d0ac0971c2e637ebddc853f12f71d130f5df4f91) -
This module introduces a memcpy DMA driver based on the DMA capabilities
of the CAAM hardware block. CAAM DMA is a platform driver that is only
probed if the device is defined in the device tree. The driver creates
a DMA channel for each JR of the CAAM. This introduces a dependency on
the JR driver. Therefore a defering mechanism was used to ensure that
the CAAM DMA driver is probed only after the JR driver.Signed-off-by: Radu Alexe
Signed-off-by: Tudor Ambarus
Signed-off-by: Rajiv Vishwakarma
Signed-off-by: Horia Geantă
29 Oct, 2020
1 commit
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This patch removes the MIC drivers from the kernel tree
since the corresponding devices have been discontinued.Removing the dma and char-misc changes in one patch and
merging via the char-misc tree is best to avoid any
potential build breakage.Cc: Nikhil Rao
Reviewed-by: Ashutosh Dixit
Signed-off-by: Sudeep Dutt
Acked-By: Vinod Koul
Reviewed-by: Sherry Sun
Link: https://lore.kernel.org/r/8c1443136563de34699d2c084df478181c205db4.1603854416.git.sudeep.dutt@intel.com
Signed-off-by: Greg Kroah-Hartman
07 Aug, 2020
1 commit
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Conflicts:
Documentation/driver-api/dmaengine/provider.rst
include/linux/dmaengine.h
17 Jul, 2020
1 commit
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The ZynqMP DisplayPort subsystem includes a DMA engine called DPDMA with
6 DMa channels (4 for display and 2 for audio). This driver exposes the
DPDMA through the dmaengine API, to be used by audio (ALSA) and display
(DRM) drivers for the DisplayPort subsystem.Signed-off-by: Hyun Kwon
Signed-off-by: Tejas Upadhyay
Signed-off-by: Michal Simek
Signed-off-by: Laurent Pinchart
Link: https://lore.kernel.org/r/20200717013337.24122-4-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul
15 Jul, 2020
1 commit
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Fix build errors when CONFIG_PCI_MSI is not enabled by making the
driver depend on PCI_MSI:ld: drivers/dma/idxd/device.o: in function `idxd_mask_msix_vector':
device.c:(.text+0x26f): undefined reference to `pci_msi_mask_irq'
ld: drivers/dma/idxd/device.o: in function `idxd_unmask_msix_vector':
device.c:(.text+0x2af): undefined reference to `pci_msi_unmask_irq'Signed-off-by: Randy Dunlap
Cc: Dave Jiang
Cc: dmaengine@vger.kernel.org
Cc: Vinod Koul
Link: https://lore.kernel.org/r/9dee3f46-70d9-ea75-10cb-5527ab297d1d@infradead.org
Signed-off-by: Vinod Koul
24 Jun, 2020
1 commit
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Kill the percpu-rwsem for work submission in favor of an sbitmap_queue.
Signed-off-by: Dave Jiang
Reviewed-by: Tony Luck
Reviewed-by: Dan Williams
Link: https://lore.kernel.org/r/159225446631.68253.8860709181621260997.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul
14 Jun, 2020
1 commit
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Since commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over
'---help---'"), the number of '---help---' has been gradually
decreasing, but there are still more than 2400 instances.This commit finishes the conversion. While I touched the lines,
I also fixed the indentation.There are a variety of indentation styles found.
a) 4 spaces + '---help---'
b) 7 spaces + '---help---'
c) 8 spaces + '---help---'
d) 1 space + 1 tab + '---help---'
e) 1 tab + '---help---' (correct indentation)
f) 1 tab + 1 space + '---help---'
g) 1 tab + 2 spaces + '---help---'In order to convert all of them to 1 tab + 'help', I ran the
following commend:$ find . -name 'Kconfig*' | xargs sed -i 's/^[[:space:]]*---help---/\thelp/'
Signed-off-by: Masahiro Yamada
11 Jun, 2020
1 commit
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Pull dmaengine updates from Vinod Koul:
"A fairly small dmaengine update which includes mostly driver updates
(dmatest, dw-edma, ioat, mmp-tdma and k3-udma) along with Renesas
binding update to json-schema"* tag 'dmaengine-5.8-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (39 commits)
dmaengine: imx-sdma: initialize all script addresses
dmaengine: ti: k3-udma: Use proper return code in alloc_chan_resources
dmaengine: ti: k3-udma: Remove udma_chan.in_ring_cnt
dmaengine: ti: k3-udma: Add missing dma_sync call for rx flush descriptor
dmaengine: at_xdmac: Replace zero-length array with flexible-array
dmaengine: at_hdmac: Replace zero-length array with flexible-array
dmaengine: qcom: bam_dma: Replace zero-length array with flexible-array
dmaengine: ti: k3-udma: Use PTR_ERR_OR_ZERO() to simplify code
dmaengine: moxart-dma: Drop pointless static qualifier in moxart_probe()
dmaengine: sf-pdma: Simplify the error handling path in 'sf_pdma_probe()'
dmaengine: qcom_hidma: use true,false for bool variable
dmaengine: dw-edma: support local dma device transfer semantics
dmaengine: Fix doc strings to satisfy validation script
dmaengine: Include dmaengine.h into dmaengine.c
dmaengine: dmatest: Describe members of struct dmatest_info
dmaengine: dmatest: Describe members of struct dmatest_params
dmaengine: dmatest: Allow negative timeout value to specify infinite wait
Revert "dmaengine: dmatest: timeout value of -1 should specify infinite wait"
dmaengine: stm32-dma: direct mode support through device tree
dt-bindings: dma: add direct mode support through device tree in stm32-dma
...
23 Apr, 2020
1 commit
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A generic SRAM will driver for Device Tree enabled platforms will do as
well.The non-DT drivers that use mmp_tdma to transfer audio samples to and from
the audio SRAM should depend on MMP_SRAM themselves.Signed-off-by: Lubomir Rintel
Link: https://lore.kernel.org/r/20200419164912.670973-8-lkundrak@v3.sk
Signed-off-by: Vinod Koul
17 Apr, 2020
1 commit
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According to https://www.analog.com/, the company name is spelled
"Analog Devices".Signed-off-by: Geert Uytterhoeven
Reviewed-by: Alexandru Ardelean
Link: https://lore.kernel.org/r/20200416103058.15269-3-geert+renesas@glider.be
[vkoul: make subsystem name dmaengine]
Signed-off-by: Vinod Koul
15 Apr, 2020
1 commit
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If PCI_MSI is not set, building fais:
drivers/dma/hisi_dma.c: In function ‘hisi_dma_free_irq_vectors’:
drivers/dma/hisi_dma.c:138:2: error: implicit declaration of function ‘pci_free_irq_vectors’;
did you mean ‘pci_alloc_irq_vectors’? [-Werror=implicit-function-declaration]
pci_free_irq_vectors(data);
^~~~~~~~~~~~~~~~~~~~Make HISI_DMA depends on PCI_MSI to fix this.
Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support")
Signed-off-by: YueHaibing
Link: https://lore.kernel.org/r/20200328114133.17560-1-yuehaibing@huawei.com
Signed-off-by: Vinod Koul
02 Mar, 2020
1 commit
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This adds external DMA controller driver implemented in Socionext
UniPhier SoCs. This driver supports DMA_MEMCPY and DMA_SLAVE modes.Since this driver does not support the the way to transfer size
unaligned to burst width, 'src_maxburst' or 'dst_maxburst' of
dma_slave_config must be 1 to transfer arbitrary size. If transfer
size is unaligned to burst size, the transfer isn't started and
the driver displays an error message.Signed-off-by: Kunihiko Hayashi
Link: https://lore.kernel.org/r/1582271550-3403-3-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Vinod Koul
25 Feb, 2020
2 commits
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There is nothing arch-specific in the driver's code, so let's enable
compile-testing for the driver.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Link: https://lore.kernel.org/r/20200209163356.6439-18-digetx@gmail.com
Signed-off-by: Vinod Koul -
The driver's removal was fixed by a recent commit and module load/unload
is working well now, tested on Tegra30.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Link: https://lore.kernel.org/r/20200209163356.6439-16-digetx@gmail.com
Signed-off-by: Vinod Koul
24 Jan, 2020
2 commits
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This patch adds a driver for HiSilicon Kunpeng DMA engine. This DMA engine
which is an PCIe iEP offers 30 channels, each channel has a send queue, a
complete queue and an interrupt to help to do tasks. This DMA engine can do
memory copy between memory blocks or between memory and device buffer.Signed-off-by: Zhou Wang
Signed-off-by: Zhenfa Qiu
Link: https://lore.kernel.org/r/1579155057-80523-1-git-send-email-wangzhou1@hisilicon.com
Signed-off-by: Vinod Koul -
The idxd driver introduces the Intel Data Stream Accelerator [1] that will
be available on future Intel Xeon CPUs. One of the kernel access
point for the driver is through the dmaengine subsystem. It will initially
provide the DMA copy service to the kernel.Some of the main functionality introduced with this accelerator
are: shared virtual memory (SVM) support, and descriptor submission using
Intel CPU instructions movdir64b and enqcmds. There will be additional
accelerator devices that share the same driver with variations to
capabilities.This commit introduces the probe and initialization component of the
driver.[1]: https://software.intel.com/en-us/download/intel-data-streaming-accelerator-preliminary-architecture-specification
Signed-off-by: Dave Jiang
Link: https://lore.kernel.org/r/157965023991.73301.6186843973135311580.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul
15 Jan, 2020
1 commit
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Some PLX Switches can expose DMA engines via extra PCI functions
on the upstream port. Each function will have one DMA channel.This patch is just the core PCI driver skeleton and dma
engine registration.Signed-off-by: Logan Gunthorpe
Link: https://lore.kernel.org/r/20200103212021.2881-2-logang@deltatee.com
Signed-off-by: Vinod Koul
22 Nov, 2019
1 commit
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Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^ /\t/' -i */KconfigSigned-off-by: Krzysztof Kozlowski
Link: https://lore.kernel.org/r/1574306348-29212-1-git-send-email-krzk@kernel.org
Signed-off-by: Vinod Koul
14 Nov, 2019
1 commit
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Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed
Rev A00 board.- Implement dmaengine APIs, support MEM_TO_MEM async copy.
- Tested by DMA Test client
- Supports 4 channels DMA, each channel has 1 done and 1 err
interrupt connected to platform-level interrupt controller (PLIC).
- Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELSThe datasheet is here:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Follow the DMAengine controller doc,
"./Documentation/driver-api/dmaengine/provider.rst" to implement DMA
engine. And use the dma test client in doc,
"./Documentation/driver-api/dmaengine/dmatest.rst", to test.Each DMA channel has separate HW regs and support done and error ISRs.
4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator
in DMA HW.------ ------
| |--< done 23 >--|ch 0|
| |--< err 24 >--| | (dma0chan0)
| | ------
| | ------
| |--< done 25 >--|ch 1|
| |--< err 26 >--| | (dma0chan1)
|PLIC| ------
| | ------
| |--< done 27 >--|ch 2|
| |--< err 28 >--| | (dma0chan2)
| | ------
| | ------
| |--< done 29 >--|ch 3|
| |--< err 30 >--| | (dma0chan3)
------ ------Signed-off-by: Green Wan
Link: https://lore.kernel.org/r/20191107084955.7580-4-green.wan@sifive.com
Signed-off-by: Vinod Koul
07 Nov, 2019
1 commit
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Add support for AXI Multichannel Direct Memory Access (AXI MCDMA)
core, which is a soft Xilinx IP core that provides high-bandwidth
direct memory access between memory and AXI4-Stream target peripherals.
The AXI MCDMA core provides scatter-gather interface with multiple
independent transmit and receive channels. The driver supports
device_prep_slave_sg slave transfer mode.Signed-off-by: Radhey Shyam Pandey
Link: https://lore.kernel.org/r/1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul
18 Oct, 2019
2 commits
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Driver for Socionext Milbeaut XDMAC controller. The controller only
supports Mem-To-Mem transfers over upto 8 configurable channels.Signed-off-by: Jassi Brar
Link: https://lore.kernel.org/r/20191015033219.14713-1-jassisinghbrar@gmail.com
Signed-off-by: Vinod Koul -
Driver for Socionext Milbeaut HDMAC controller. The controller has
upto 8 floating channels, that need a predefined slave-id to work
from a set of slaves.Signed-off-by: Jassi Brar
Link: https://lore.kernel.org/r/20191015033359.14925-1-jassisinghbrar@gmail.com
Signed-off-by: Vinod Koul
17 Oct, 2019
1 commit
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DPPA2(Data Path Acceleration Architecture 2) qDMA supports
virtualized channel by allowing DMA jobs to be enqueued into
different work queues. Core can initiate a DMA transaction by
preparing a frame descriptor(FD) for each DMA job and enqueuing
this job through a hardware portal. DPAA2 components can also
prepare a FD and enqueue a DMA job through a hardware portal.
The qDMA prefetches DMA jobs through DPAA2 hardware portal. It
then schedules and dispatches to internal DMA hardware engines,
which generate read and write requests. Both qDMA source data and
destination data can be either contiguous or non-contiguous using
one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all DMA
transactions are stalled if the bandwidth threshold has been reached.
Also supported are transaction based read throttling.Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.Signed-off-by: Peng Ma
Link: https://lore.kernel.org/r/20190930020440.7754-2-peng.ma@nxp.com
Signed-off-by: Vinod Koul
23 Sep, 2019
1 commit
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Pull MIPS updates from Paul Burton:
"Main MIPS changes:- boot_mem_map is removed, providing a nice cleanup made possible by
the recent removal of bootmem.- Some fixes to atomics, in general providing compiler barriers for
smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs
or MIPS32 systems using cmpxchg64().- Conversion to the new generic VDSO infrastructure courtesy of
Vincenzo Frascino.- Removal of undefined behavior in set_io_port_base(), fixing the
behavior of some MIPS kernel configurations when built with recent
clang versions.- Initial MIPS32 huge page support, functional on at least Ingenic
SoCs.- pte_special() is now supported for some configurations, allowing
among other things generic fast GUP to be used.- Miscellaneous fixes & cleanups.
And platform specific changes:
- Major improvements to Ingenic SoC support from Paul Cercueil,
mostly enabled by the inclusion of the new TCU (timer-counter unit)
drivers he's spent a very patient year or so working on. Plus some
fixes for X1000 SoCs from Zhou Yanjie.- Netgear R6200 v1 systems are now supported by the bcm47xx platform.
- DT updates for BMIPS, Lantiq & Microsemi Ocelot systems"
* tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (89 commits)
MIPS: Detect bad _PFN_SHIFT values
MIPS: Disable pte_special() for MIPS32 with RiXi
MIPS: ralink: deactivate PCI support for SOC_MT7621
mips: compat: vdso: Use legacy syscalls as fallback
MIPS: Drop Loongson _CACHE_* definitions
MIPS: tlbex: Remove cpu_has_local_ebase
MIPS: tlbex: Simplify r3k check
MIPS: Select R3k-style TLB in Kconfig
MIPS: PCI: refactor ioc3 special handling
mips: remove ioremap_cachable
mips/atomic: Fix smp_mb__{before,after}_atomic()
mips/atomic: Fix loongson_llsc_mb() wreckage
mips/atomic: Fix cmpxchg64 barriers
MIPS: Octeon: remove duplicated include from dma-octeon.c
firmware: bcm47xx_nvram: Allow COMPILE_TEST
firmware: bcm47xx_nvram: Correct size_t printf format
MIPS: Treat Loongson Extensions as ASEs
MIPS: Remove dev_err() usage after platform_get_irq()
MIPS: dts: mscc: describe the PTP ready interrupt
MIPS: dts: mscc: describe the PTP register range
...
18 Sep, 2019
1 commit
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Pull dmaengine updates from Vinod Koul:
- Move Dmaengine DT bindings to YAML and convert Allwinner to schema.
- FSL dma device_synchronize implementation
- DW split acpi and of helpers and updates to driver and support for
Elkhart Lake- Move filter fn as private for omap-dma and edma drivers and
improvements to these drivers- Mark expected switch fall-through in couple of drivers
- Renames of shdma and nbpfaxi binding document
- Minor updates to bunch of drivers
* tag 'dmaengine-5.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (55 commits)
dmaengine: ti: edma: Use bitmap_set() instead of open coded edma_set_bits()
dmaengine: ti: edma: Only reset region0 access registers
dmaengine: ti: edma: Do not reset reserved paRAM slots
dmaengine: iop-adma.c: fix printk format warning
dmaengine: stm32-dma: Use struct_size() helper
dt-bindings: dmaengine: dma-common: Fix the dma-channel-mask property
dmanegine: ioat/dca: Use struct_size() helper
dmaengine: iop-adma: remove set but not used variable 'slots_per_op'
dmaengine: dmatest: Add support for completion polling
dmaengine: ti: omap-dma: Remove variable override in omap_dma_tx_status()
dmaengine: ti: omap-dma: Remove 'Assignment in if condition'
dmaengine: ti: edma: Remove 'Assignment in if condition'
dmaengine: dw: platform: Split OF helpers to separate module
dmaengine: dw: platform: Split ACPI helpers to separate module
dmaengine: dw: platform: Move handle check to dw_dma_acpi_controller_register()
dmaengine: dw: platform: Switch to acpi_dma_controller_register()
dmaengine: dw: platform: Use devm_platform_ioremap_resource()
dmaengine: dw: platform: Enable iDMA 32-bit on Intel Elkhart Lake
dmaengine: dw: platform: Use struct dw_dma_chip_pdata
dmaengine: dw: Export struct dw_dma_chip_pdata for wider use
...
17 Sep, 2019
1 commit
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Pull ARM SoC platform updates from Arnd Bergmann:
"The main change this time around is a cleanup of some of the oldest
platforms based on the XScale and ARM9 CPU cores, which are between 10
and 20 years old.The Kendin/Micrel/Microchip KS8695, Winbond/Nuvoton W90x900 and Intel
IOP33x/IOP13xx platforms are removed after we determined that nobody
is using them any more.The TI Davinci and NXP LPC32xx platforms on the other hand are still
in active use and are converted to the ARCH_MULTIPLATFORM build,
meaning that we can compile a kernel that works on these along with
most other ARMv5 platforms. Changes toward that goal are also merged
for IOP32x, but additional work is needed to complete this. Patches
for the remaining ARMv5 platforms have started but need more work and
some testing.Support for the new ASpeed AST2600 gets added, this is based on the
Cortex-A7 ARMv7 core, and is a newer version of the existing ARMv5 and
ARMv6 chips in the same family.Other changes include a cleanup of the ST-Ericsson ux500 platform and
the move of the TI Davinci platform to a new clocksource driver"[ The changes had marked INTEL_IOP_ADMA and USB_LPC32XX as being
buildable on other platforms through COMPILE_TEST, but that causes new
warnings that I most definitely do not want to see during the merge
window as that could hide other issues.So the COMPILE_TEST option got disabled for them again - Linus ]
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits)
ARM: multi_v5_defconfig: make DaVinci part of the ARM v5 multiplatform build
ARM: davinci: support multiplatform build for ARM v5
arm64: exynos: Enable exynos-chipid driver
ARM: OMAP2+: Delete an unnecessary kfree() call in omap_hsmmc_pdata_init()
ARM: OMAP2+: move platform-specific asm-offset.h to arch/arm/mach-omap2
ARM: davinci: dm646x: Fix a typo in the comment
ARM: davinci: dm646x: switch to using the clocksource driver
ARM: davinci: dm644x: switch to using the clocksource driver
ARM: aspeed: Enable SMP boot
ARM: aspeed: Add ASPEED AST2600 architecture
ARM: aspeed: Select timer in each SoC
dt-bindings: arm: cpus: Add ASPEED SMP
ARM: imx: stop adjusting ar8031 phy tx delay
mailmap: map old company name to new one @microchip.com
MAINTAINERS: at91: remove the TC entry
MAINTAINERS: at91: Collect all pinctrl/gpio drivers in same entry
ARM: at91: move platform-specific asm-offset.h to arch/arm/mach-at91
MAINTAINERS: Extend patterns for Samsung SoC, Security Subsystem and clock drivers
ARM: s3c64xx: squash samsung_usb_phy.h into setup-usb-phy.c
ARM: debug-ll: Add support for r7s9210
...
14 Aug, 2019
2 commits
-
Now that iop3xx and iop13xx are gone, the iop-adma driver no
longer needs to deal with incompatible register layout defined
in machine specific header files.Move the iop32x specific definitions into drivers/dma/iop-adma.h
and the platform_data into include/linux/platform_data/dma-iop32x.h,
and change the machine code to no longer reference those.The DMA0_ID/DMA1_ID/AAU_ID macros are required as part of the
platform data interface and still need to be visible, so move
those from one header to the other.Link: https://lore.kernel.org/r/20190809163334.489360-4-arnd@arndb.de
Signed-off-by: Arnd Bergmann -
There are three families of IOP machines we support in Linux: iop32x
(which includes EP80219), iop33x and iop13xx (aka IOP34x aka WP8134x).All products we support in the kernel are based on the first of these,
iop32x, the other families only ever supported the Intel reference
boards but no actual machine anyone could ever buy.While one could clearly make them all three work in a single kernel
with some work, this takes the easy way out, removing the later two
platforms entirely, under the assumption that there are no remaining
users.Earlier versions of OpenWRT and Debian both had support for iop32x
but not the others, and they both dropped iop32x as well in their 2015
releases.Link: https://lore.kernel.org/r/20190809163334.489360-1-arnd@arndb.de
Signed-off-by: Arnd Bergmann
Acked-by: Wolfram Sang # for I2C parts
Acked-by: Dan Williams
Acked-by: Martin Michlmayr
Signed-off-by: Arnd Bergmann
31 Jul, 2019
1 commit
-
The newer and better JZ4780 driver is now used to provide DMA
functionality on the JZ4740.Signed-off-by: Paul Cercueil
Tested-by: Artur Rojek
Acked-by: Vinod Koul
Signed-off-by: Paul Burton
18 Jul, 2019
1 commit
-
Pull dmaengine updates from Vinod Koul:
- Add support in dmaengine core to do device node checks for DT devices
and update bunch of drivers to use that and remove open coding from
drivers- New driver/driver support for new hardware, namely:
- MediaTek UART APDMA
- Freescale i.mx7ulp edma2
- Synopsys eDMA IP core version 0
- Allwinner H6 DMA- Updates to axi-dma and support for interleaved cyclic transfers
- Greg's debugfs return value check removals on drivers
- Updates to stm32-dma, hsu, dw, pl330, tegra drivers
* tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (68 commits)
dmaengine: Revert "dmaengine: fsl-edma: add i.mx7ulp edma2 version support"
dmaengine: at_xdmac: check for non-empty xfers_list before invoking callback
Documentation: dmaengine: clean up description of dmatest usage
dmaengine: tegra210-adma: remove PM_CLK dependency
dmaengine: fsl-edma: add i.mx7ulp edma2 version support
dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma
dmaengine: fsl-edma-common: version check for v2 instead
dmaengine: fsl-edma-common: move dmamux register to another single function
dmaengine: fsl-edma: add drvdata for fsl-edma
dmaengine: Revert "dmaengine: fsl-edma: support little endian for edma driver"
dmaengine: rcar-dmac: Reject zero-length slave DMA requests
dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake
dmaengine: dw-edma: fix semicolon.cocci warnings
dmaengine: sh: usb-dmac: Use [] to denote a flexible array member
dmaengine: dmatest: timeout value of -1 should specify infinite wait
dmaengine: dw: Distinguish ->remove() between DW and iDMA 32-bit
dmaengine: fsl-edma: support little endian for edma driver
dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width"
dmagengine: pl330: add code to get reset property
dt-bindings: pl330: document the optional resets property
...
05 Jul, 2019
1 commit
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Tegra ADMA does not use pm-clk interface now and hence the dependency
is removed from Kconfig.Signed-off-by: Sameer Pujar
Acked-by: Jon Hunter
Signed-off-by: Vinod Koul
14 Jun, 2019
1 commit
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The registers for AXI DMAC are detailed at:
https://wiki.analog.com/resources/fpga/docs/axi_dmac#register_mapThis change adds regmap support for these registers, in case some wants to
have a more direct access to them via this interface.Signed-off-by: Alexandru Ardelean
[vkoul: fixed code style issue]
Signed-off-by: Vinod Koul
10 Jun, 2019
1 commit
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Add Synopsys PCIe Endpoint eDMA IP core driver to kernel.
This IP is generally distributed with Synopsys PCIe Endpoint IP (depends
of the use and licensing agreement).This core driver, initializes and configures the eDMA IP using vma-helpers
functions and dma-engine subsystem.This driver can be compile as built-in or external module in kernel.
To enable this driver just select DW_EDMA option in kernel configuration,
however it requires and selects automatically DMA_ENGINE and
DMA_VIRTUAL_CHANNELS option too.In order to transfer data from point A to B as fast as possible this IP
requires a dedicated memory space containing linked list of elements.All elements of this linked list are continuous and each one describes a
data transfer (source and destination addresses, length and a control
variable).For the sake of simplicity, lets assume a memory space for channel write
0 which allows about 42 elements.+---------+
| Desc #0 |-+
+---------+ |
V
+----------+
| Chunk #0 |-+
| CB = 1 | | +----------+ +-----+ +-----------+ +-----+
+----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp |
| +----------+ +-----+ +-----------+ +-----+
V
+----------+
| Chunk #1 |-+
| CB = 0 | | +-----------+ +-----+ +-----------+ +-----+
+----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp |
| +-----------+ +-----+ +-----------+ +-----+
V
+----------+
| Chunk #2 |-+
| CB = 1 | | +-----------+ +-----+ +------------+ +-----+
+----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp |
| +-----------+ +-----+ +------------+ +-----+
V
+----------+
| Chunk #3 |-+
| CB = 0 | | +------------+ +-----+ +------------+ +-----+
+----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp |
+------------+ +-----+ +------------+ +-----+Legend:
- Linked list, also know as Chunk
- Linked list element*, also know as Burst *CB*, also know as Change Bit,
it's a control bit (and typically is toggled) that allows to easily
identify and differentiate between the current linked list and the
previous or the next one.
- LLP, is a special element that indicates the end of the linked list
element stream also informs that the next CB should be toggleOn every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 or
even Burst #129) is set some flags on their control variable (RIE and
LIE bits) that will trigger the send of "done" interruption.On the interruptions callback, is decided whether to recycle the linked
list memory space by writing a new set of Bursts elements (if still
exists Chunks to transfer) or is considered completed (if there is no
Chunks available to transfer).On scatter-gather transfer mode, the client will submit a scatter-gather
list of n (on this case 130) elements, that will be divide in multiple
Chunks, each Chunk will have (on this case 42) a limited number of
Bursts and after transferring all Bursts, an interrupt will be
triggered, which will allow to recycle the all linked list dedicated
memory again with the new information relative to the next Chunk and
respective Burst associated and repeat the whole cycle again.On cyclic transfer mode, the client will submit a buffer pointer, length
of it and number of repetitions, in this case each burst will correspond
directly to each repetition.Each Burst can describes a data transfer from point A(source) to point
B(destination) with a length that can be from 1 byte up to 4 GB. Since
dedicated the memory space where the linked list will reside is limited,
the whole n burst elements will be organized in several Chunks, that
will be used later to recycle the dedicated memory space to initiate a
new sequence of data transfers.The whole transfer is considered has completed when it was transferred
all bursts.Currently this IP has a set well-known register map, which includes
support for legacy and unroll modes. Legacy mode is version of this
register map that has multiplexer register that allows to switch
registers between all write and read channels and the unroll modes
repeats all write and read channels registers with an offset between
them. This register map is called v0.The IP team is creating a new register map more suitable to the latest
PCIe features, that very likely will change the map register, which this
version will be called v1. As soon as this new version is released by
the IP team the support for this version in be included on this driver.According to the logic, patches 1, 2 and 3 should be squashed into 1
unique patch, but for the sake of simplicity of review, it was divided
in this 3 patches files.Signed-off-by: Gustavo Pimentel
Cc: Vinod Koul
Cc: Dan Williams
Cc: Andy Shevchenko
Cc: Russell King
Cc: Joao Pinto
Signed-off-by: Vinod Koul
21 May, 2019
1 commit
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Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:GPL-2.0-only
Signed-off-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
26 Mar, 2019
1 commit
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The AXI DMAC driver is currently supported also on the Xilinx ZynqMP
architecture. This change allows this driver to be enabled & used on it as
well.Signed-off-by: Michael Hennerich
Signed-off-by: Alexandru Ardelean
Signed-off-by: Vinod Koul
07 Jan, 2019
1 commit
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NXP Queue DMA controller(qDMA) on Layerscape SoCs supports channel
virtuallization by allowing DMA jobs to be enqueued into different
command queues.Signed-off-by: Wen He
Signed-off-by: Jiaheng Fan
Signed-off-by: Peng Ma
Signed-off-by: Vinod Koul