Eric Lee / smarc-fsl-linux-kernel

18 Dec, 2020

2 commits

  • b231f3359   Merge branch 'pxp/next' into next ... Browse Code »

    * pxp/next: (8 commits)
    LF-1596 dma: pxp: add checking for out against NULL
    LF-1595 dma: pxp: fix the typo for possible_inputs_s1 checking
    LF-1594 dma: pxp: fix out-of-bounds access
    LF-1162-19 media: mxc: pxp_v4l2: change to use VFL_TYPE_VIDEO
    LF-105-1 dmaengine: pxp: fix build warning of fall through
    ...

    BJ DevOps Team
     
  • 87467a86f   Merge remote-tracking branch 'origin/dma/edma' into dma/next ... Browse Code »

    * origin/dma/edma: (31 commits)
    MLK-24825-2: dmaengine: fsl-edma: checking ACTIVE bit for channel stop
    MLK-24825-1: dmaengine: fsl-edma-v3: checking ACTIVE bit for channel stop
    MLK-24292: dmaengine: fsl-edma-v3: correct power domain attach checking
    LF-631-2 dt-bindings: fsl-edma: Document support for S32V234
    LF-631-4 dmaengine: fsl-edma: Add support for S32V234
    ...

    BJ DevOps Team
     

14 Dec, 2020

3 commits

29 Oct, 2020

1 commit

  • 80ade22c0   misc: mic: remove the MIC drivers ... Browse Code »

    This patch removes the MIC drivers from the kernel tree
    since the corresponding devices have been discontinued.

    Removing the dma and char-misc changes in one patch and
    merging via the char-misc tree is best to avoid any
    potential build breakage.

    Cc: Nikhil Rao
    Reviewed-by: Ashutosh Dixit
    Signed-off-by: Sudeep Dutt
    Acked-By: Vinod Koul
    Reviewed-by: Sherry Sun
    Link: https://lore.kernel.org/r/8c1443136563de34699d2c084df478181c205db4.1603854416.git.sudeep.dutt@intel.com
    Signed-off-by: Greg Kroah-Hartman

    Sudeep Dutt
     

02 Mar, 2020

1 commit

  • 667b92514   dmaengine: uniphier-xdmac: Add UniPhier external DMA controller driver ... Browse Code »

    This adds external DMA controller driver implemented in Socionext
    UniPhier SoCs. This driver supports DMA_MEMCPY and DMA_SLAVE modes.

    Since this driver does not support the the way to transfer size
    unaligned to burst width, 'src_maxburst' or 'dst_maxburst' of
    dma_slave_config must be 1 to transfer arbitrary size. If transfer
    size is unaligned to burst size, the transfer isn't started and
    the driver displays an error message.

    Signed-off-by: Kunihiko Hayashi
    Link: https://lore.kernel.org/r/1582271550-3403-3-git-send-email-hayashi.kunihiko@socionext.com
    Signed-off-by: Vinod Koul

    Kunihiko Hayashi
     

24 Jan, 2020

2 commits

  • e9f08b652   dmaengine: hisilicon: Add Kunpeng DMA engine support ... Browse Code »

    This patch adds a driver for HiSilicon Kunpeng DMA engine. This DMA engine
    which is an PCIe iEP offers 30 channels, each channel has a send queue, a
    complete queue and an interrupt to help to do tasks. This DMA engine can do
    memory copy between memory blocks or between memory and device buffer.

    Signed-off-by: Zhou Wang
    Signed-off-by: Zhenfa Qiu
    Link: https://lore.kernel.org/r/1579155057-80523-1-git-send-email-wangzhou1@hisilicon.com
    Signed-off-by: Vinod Koul

    Zhou Wang
     
  • bfe1d5609   dmaengine: idxd: Init and probe for Intel data accelerators ... Browse Code »

    The idxd driver introduces the Intel Data Stream Accelerator [1] that will
    be available on future Intel Xeon CPUs. One of the kernel access
    point for the driver is through the dmaengine subsystem. It will initially
    provide the DMA copy service to the kernel.

    Some of the main functionality introduced with this accelerator
    are: shared virtual memory (SVM) support, and descriptor submission using
    Intel CPU instructions movdir64b and enqcmds. There will be additional
    accelerator devices that share the same driver with variations to
    capabilities.

    This commit introduces the probe and initialization component of the
    driver.

    [1]: https://software.intel.com/en-us/download/intel-data-streaming-accelerator-preliminary-architecture-specification

    Signed-off-by: Dave Jiang
    Link: https://lore.kernel.org/r/157965023991.73301.6186843973135311580.stgit@djiang5-desk3.ch.intel.com
    Signed-off-by: Vinod Koul

    Dave Jiang
     

15 Jan, 2020

1 commit

14 Nov, 2019

1 commit

  • 6973886ad   dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 ... Browse Code »

    Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed
    Rev A00 board.

    - Implement dmaengine APIs, support MEM_TO_MEM async copy.
    - Tested by DMA Test client
    - Supports 4 channels DMA, each channel has 1 done and 1 err
    interrupt connected to platform-level interrupt controller (PLIC).
    - Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS

    The datasheet is here:

    https://static.dev.sifive.com/FU540-C000-v1.0.pdf

    Follow the DMAengine controller doc,
    "./Documentation/driver-api/dmaengine/provider.rst" to implement DMA
    engine. And use the dma test client in doc,
    "./Documentation/driver-api/dmaengine/dmatest.rst", to test.

    Each DMA channel has separate HW regs and support done and error ISRs.
    4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator
    in DMA HW.

    ------ ------
    | |--< done 23 >--|ch 0|
    | |--< err 24 >--| | (dma0chan0)
    | | ------
    | | ------
    | |--< done 25 >--|ch 1|
    | |--< err 26 >--| | (dma0chan1)
    |PLIC| ------
    | | ------
    | |--< done 27 >--|ch 2|
    | |--< err 28 >--| | (dma0chan2)
    | | ------
    | | ------
    | |--< done 29 >--|ch 3|
    | |--< err 30 >--| | (dma0chan3)
    ------ ------

    Signed-off-by: Green Wan
    Link: https://lore.kernel.org/r/20191107084955.7580-4-green.wan@sifive.com
    Signed-off-by: Vinod Koul

    Green Wan
     

18 Oct, 2019

2 commits

17 Oct, 2019

1 commit

  • 7fdf9b05c   dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs ... Browse Code »

    DPPA2(Data Path Acceleration Architecture 2) qDMA supports
    virtualized channel by allowing DMA jobs to be enqueued into
    different work queues. Core can initiate a DMA transaction by
    preparing a frame descriptor(FD) for each DMA job and enqueuing
    this job through a hardware portal. DPAA2 components can also
    prepare a FD and enqueue a DMA job through a hardware portal.
    The qDMA prefetches DMA jobs through DPAA2 hardware portal. It
    then schedules and dispatches to internal DMA hardware engines,
    which generate read and write requests. Both qDMA source data and
    destination data can be either contiguous or non-contiguous using
    one or more scatter/gather tables.
    The qDMA supports global bandwidth flow control where all DMA
    transactions are stalled if the bandwidth threshold has been reached.
    Also supported are transaction based read throttling.

    Add NXP dppa2 qDMA to support some of Layerscape SoCs.
    such as: LS1088A, LS208xA, LX2, etc.

    Signed-off-by: Peng Ma
    Link: https://lore.kernel.org/r/20190930020440.7754-2-peng.ma@nxp.com
    Signed-off-by: Vinod Koul

    Peng Ma
     

31 Jul, 2019

1 commit

  • 091c6104a   dma: Drop JZ4740 driver ... Browse Code »

    The newer and better JZ4780 driver is now used to provide DMA
    functionality on the JZ4740.

    Signed-off-by: Paul Cercueil
    Tested-by: Artur Rojek
    Acked-by: Vinod Koul
    Signed-off-by: Paul Burton

    Paul Cercueil
     

10 Jun, 2019

1 commit

  • e63d79d1f   dmaengine: Add Synopsys eDMA IP core driver ... Browse Code »

    Add Synopsys PCIe Endpoint eDMA IP core driver to kernel.

    This IP is generally distributed with Synopsys PCIe Endpoint IP (depends
    of the use and licensing agreement).

    This core driver, initializes and configures the eDMA IP using vma-helpers
    functions and dma-engine subsystem.

    This driver can be compile as built-in or external module in kernel.

    To enable this driver just select DW_EDMA option in kernel configuration,
    however it requires and selects automatically DMA_ENGINE and
    DMA_VIRTUAL_CHANNELS option too.

    In order to transfer data from point A to B as fast as possible this IP
    requires a dedicated memory space containing linked list of elements.

    All elements of this linked list are continuous and each one describes a
    data transfer (source and destination addresses, length and a control
    variable).

    For the sake of simplicity, lets assume a memory space for channel write
    0 which allows about 42 elements.

    +---------+
    | Desc #0 |-+
    +---------+ |
    V
    +----------+
    | Chunk #0 |-+
    | CB = 1 | | +----------+ +-----+ +-----------+ +-----+
    +----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp |
    | +----------+ +-----+ +-----------+ +-----+
    V
    +----------+
    | Chunk #1 |-+
    | CB = 0 | | +-----------+ +-----+ +-----------+ +-----+
    +----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp |
    | +-----------+ +-----+ +-----------+ +-----+
    V
    +----------+
    | Chunk #2 |-+
    | CB = 1 | | +-----------+ +-----+ +------------+ +-----+
    +----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp |
    | +-----------+ +-----+ +------------+ +-----+
    V
    +----------+
    | Chunk #3 |-+
    | CB = 0 | | +------------+ +-----+ +------------+ +-----+
    +----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp |
    +------------+ +-----+ +------------+ +-----+

    Legend:
    - Linked list, also know as Chunk
    - Linked list element*, also know as Burst *CB*, also know as Change Bit,
    it's a control bit (and typically is toggled) that allows to easily
    identify and differentiate between the current linked list and the
    previous or the next one.
    - LLP, is a special element that indicates the end of the linked list
    element stream also informs that the next CB should be toggle

    On every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 or
    even Burst #129) is set some flags on their control variable (RIE and
    LIE bits) that will trigger the send of "done" interruption.

    On the interruptions callback, is decided whether to recycle the linked
    list memory space by writing a new set of Bursts elements (if still
    exists Chunks to transfer) or is considered completed (if there is no
    Chunks available to transfer).

    On scatter-gather transfer mode, the client will submit a scatter-gather
    list of n (on this case 130) elements, that will be divide in multiple
    Chunks, each Chunk will have (on this case 42) a limited number of
    Bursts and after transferring all Bursts, an interrupt will be
    triggered, which will allow to recycle the all linked list dedicated
    memory again with the new information relative to the next Chunk and
    respective Burst associated and repeat the whole cycle again.

    On cyclic transfer mode, the client will submit a buffer pointer, length
    of it and number of repetitions, in this case each burst will correspond
    directly to each repetition.

    Each Burst can describes a data transfer from point A(source) to point
    B(destination) with a length that can be from 1 byte up to 4 GB. Since
    dedicated the memory space where the linked list will reside is limited,
    the whole n burst elements will be organized in several Chunks, that
    will be used later to recycle the dedicated memory space to initiate a
    new sequence of data transfers.

    The whole transfer is considered has completed when it was transferred
    all bursts.

    Currently this IP has a set well-known register map, which includes
    support for legacy and unroll modes. Legacy mode is version of this
    register map that has multiplexer register that allows to switch
    registers between all write and read channels and the unroll modes
    repeats all write and read channels registers with an offset between
    them. This register map is called v0.

    The IP team is creating a new register map more suitable to the latest
    PCIe features, that very likely will change the map register, which this
    version will be called v1. As soon as this new version is released by
    the IP team the support for this version in be included on this driver.

    According to the logic, patches 1, 2 and 3 should be squashed into 1
    unique patch, but for the sake of simplicity of review, it was divided
    in this 3 patches files.

    Signed-off-by: Gustavo Pimentel
    Cc: Vinod Koul
    Cc: Dan Williams
    Cc: Andy Shevchenko
    Cc: Russell King
    Cc: Joao Pinto
    Signed-off-by: Vinod Koul

    Gustavo Pimentel
     

07 Jan, 2019

1 commit

24 Nov, 2018

1 commit

11 Sep, 2018

2 commits

09 Aug, 2018

1 commit

25 Apr, 2018

1 commit

10 Apr, 2018

1 commit

27 Mar, 2018

1 commit

  • 548c4597e   dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC ... Browse Code »

    MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has
    a single ring is dedicated to memory-to-memory transfer through ring based
    descriptor management.

    Even though there is only one physical ring available inside HSDMA, the
    driver can be easily extended to the support of multiple virtual channels
    processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort.

    Signed-off-by: Sean Wang
    Cc: Randy Dunlap
    Cc: Fengguang Wu
    Cc: Julia Lawall
    Signed-off-by: Vinod Koul

    Sean Wang
     

19 Mar, 2018

1 commit

15 Nov, 2017

1 commit

  • 23c258763   Merge tag 'dmaengine-4.15-rc1' of git://git.infradead.org/users/vkoul/slave-dma ... Browse Code »

    Pull dmaengine updates from Vinod Koul:
    "Updates for this cycle include:

    - new driver for Spreadtrum dma controller, ST MDMA and DMAMUX
    controllers

    - PM support for IMG MDC drivers

    - updates to bcm-sba-raid driver and improvements to sun6i driver

    - subsystem conversion for:
    - timers to use timer_setup()
    - remove usage of PCI pool API
    - usage of %p format specifier

    - minor updates to bunch of drivers"

    * tag 'dmaengine-4.15-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (49 commits)
    dmaengine: ti-dma-crossbar: Correct am335x/am43xx mux value type
    dmaengine: dmatest: warn user when dma test times out
    dmaengine: Revert "rcar-dmac: use TCRB instead of TCR for residue"
    dmaengine: stm32_mdma: activate pack/unpack feature
    dmaengine: at_hdmac: Remove unnecessary 0x prefixes before %pad
    dmaengine: coh901318: Remove unnecessary 0x prefixes before %pad
    MAINTAINERS: Step down from a co-maintaner of DW DMAC driver
    dmaengine: pch_dma: Replace PCI pool old API
    dmaengine: Convert timers to use timer_setup()
    dmaengine: sprd: Add Spreadtrum DMA driver
    dt-bindings: dmaengine: Add Spreadtrum SC9860 DMA controller
    dmaengine: sun6i: Retrieve channel count/max request from devicetree
    dmaengine: Build bcm-sba-raid driver as loadable module for iProc SoCs
    dmaengine: bcm-sba-raid: Use common GPL comment header
    dmaengine: bcm-sba-raid: Use only single mailbox channel
    dmaengine: bcm-sba-raid: serialize dma_cookie_complete() using reqs_lock
    dmaengine: pl330: fix descriptor allocation fail
    dmaengine: rcar-dmac: use TCRB instead of TCR for residue
    dmaengine: sun6i: Add support for Allwinner A64 and compatibles
    arm64: allwinner: a64: Add devicetree binding for DMA controller
    ...

    Linus Torvalds
     

14 Nov, 2017

1 commit

02 Nov, 2017

1 commit

  • b24413180   License cleanup: add SPDX GPL-2.0 license identifier to files with no license ... Browse Code »

    Many source files in the tree are missing licensing information, which
    makes it harder for compliance tools to determine the correct license.

    By default all files without license information are under the default
    license of the kernel, which is GPL version 2.

    Update the files which contain no license information with the 'GPL-2.0'
    SPDX license identifier. The SPDX identifier is a legally binding
    shorthand, which can be used instead of the full boiler plate text.

    This patch is based on work done by Thomas Gleixner and Kate Stewart and
    Philippe Ombredanne.

    How this work was done:

    Patches were generated and checked against linux-4.14-rc6 for a subset of
    the use cases:
    - file had no licensing information it it.
    - file was a */uapi/* one with no licensing information in it,
    - file was a */uapi/* one with existing licensing information,

    Further patches will be generated in subsequent months to fix up cases
    where non-standard license headers were used, and references to license
    had to be inferred by heuristics based on keywords.

    The analysis to determine which SPDX License Identifier to be applied to
    a file was done in a spreadsheet of side by side results from of the
    output of two independent scanners (ScanCode & Windriver) producing SPDX
    tag:value files created by Philippe Ombredanne. Philippe prepared the
    base worksheet, and did an initial spot review of a few 1000 files.

    The 4.13 kernel was the starting point of the analysis with 60,537 files
    assessed. Kate Stewart did a file by file comparison of the scanner
    results in the spreadsheet to determine which SPDX license identifier(s)
    to be applied to the file. She confirmed any determination that was not
    immediately clear with lawyers working with the Linux Foundation.

    Criteria used to select files for SPDX license identifier tagging was:
    - Files considered eligible had to be source code files.
    - Make and config files were included as candidates if they contained >5
    lines of source
    - File already had some variant of a license header in it (even if
    Reviewed-by: Philippe Ombredanne
    Reviewed-by: Thomas Gleixner
    Signed-off-by: Greg Kroah-Hartman

    Greg Kroah-Hartman
     

24 Oct, 2017

1 commit

08 Oct, 2017

1 commit

  • a4ffb13c8   dmaengine: Add STM32 MDMA driver ... Browse Code »

    This patch adds the driver for the STM32 MDMA controller.

    Master Direct memory access (MDMA) is used in order to provide high-speed
    data transfer between memory and memory or between peripherals and memory.

    MDMA controller provides a master AXI interface for main memory and
    peripheral registers access (system access port) and a master AHB
    interface only for Cortex-M7 TCM memory access (TCM access port).

    MDMA works in conjunction with the standard DMA controllers (DMA1 or DMA2).
    It offers up to 64 channels, each dedicated to managing memory access
    requests from one of the DMA stream memory buffer or other peripherals
    (w/ integrated FIFO).

    Signed-off-by: M'boumba Cedric Madianga
    Signed-off-by: Pierre-Yves MORDRET
    Signed-off-by: Vinod Koul

    Pierre-Yves MORDRET
     

27 Sep, 2017

1 commit

  • df7e762db   dmaengine: Add STM32 DMAMUX driver ... Browse Code »

    This patch implements the STM32 DMAMUX driver.

    The DMAMUX request multiplexer allows routing a DMA request line between
    the peripherals and the DMA controllers of the product. The routing
    function is ensured by a programmable multi-channel DMA request line
    multiplexer. Each channel selects a unique DMA request line,
    unconditionally or synchronously with events from its DMAMUX
    synchronization inputs. The DMAMUX may also be used as a DMA request
    generator from programmable events on its input trigger signals

    Signed-off-by: M'boumba Cedric Madianga
    Signed-off-by: Pierre-Yves MORDRET
    Signed-off-by: Vinod Koul

    Pierre-Yves MORDRET
     

19 Jul, 2017

1 commit

  • a85c6f1b2   dmaengine: Add driver for Altera / Intel mSGDMA IP core ... Browse Code »

    This driver adds support for the Altera / Intel modular Scatter-Gather
    Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux
    DMAengine subsystem. Currently it supports the following op modes:

    - DMA_MEMCPY
    - DMA_SG
    - DMA_SLAVE

    This implementation has been tested on an Altera Cyclone FPGA connected
    via PCIe, both on an ARM and an x86 platform.

    Signed-off-by: Stefan Roese
    Cc: Vinod Koul
    Signed-off-by: Vinod Koul

    Stefan Roese
     

16 May, 2017

1 commit

  • 743e1c8ff   dmaengine: Add Broadcom SBA RAID driver ... Browse Code »

    The Broadcom stream buffer accelerator (SBA) provides offloading
    capabilities for RAID operations. This SBA offload engine is
    accessible via Broadcom SoC specific ring manager.

    This patch adds Broadcom SBA RAID driver which provides one
    DMA device with RAID capabilities using one or more Broadcom
    SoC specific ring manager channels. The SBA RAID driver in its
    current shape implements memcpy, xor, and pq operations.

    Signed-off-by: Anup Patel
    Reviewed-by: Ray Jui
    Acked-by: Dan Williams
    Signed-off-by: Vinod Koul

    Anup Patel
     

02 Jan, 2017

1 commit

18 Oct, 2016

1 commit

  • 6b4cd727e   dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support ... Browse Code »

    This patch adds support for the Flexible Direct Memory Access (FDMA) core
    driver. The FDMA is a slim core CPU with a dedicated firmware.
    It is a general purpose DMA controller capable of supporting 16
    independent DMA channels. Data moves maybe from memory to memory
    or between memory and paced latency critical real time targets and it
    is found on al STi based chipsets.

    Signed-off-by: Ludovic Barre
    Signed-off-by: Peter Griffin
    Signed-off-by: Vinod Koul

    Peter Griffin
     

12 Jul, 2016

1 commit

  • 19a340b1a   dmaengine: mv_xor_v2: new driver ... Browse Code »

    The new mv_xor_v2 driver supports the XOR engines found in the 64-bits
    ARM from Marvell of the Armada 7K and Armada 8K family. This XOR
    engine is a completely new hardware block, entirely different from the
    one used on previous Marvell Armada platforms, which use the existing
    mv_xor driver.

    Signed-off-by: Thomas Petazzoni
    Signed-off-by: Vinod Koul

    Thomas Petazzoni
     

13 May, 2016

1 commit

  • f46b19579   dmaengine: tegra-adma: Add support for Tegra210 ADMA ... Browse Code »

    Add support for the Tegra210 Audio DMA controller that is used for
    transferring data between system memory and the Audio sub-system.
    The driver only supports cyclic transfers because this is being solely
    used for audio.

    This driver is based upon the work by Dara Ramesh .

    Signed-off-by: Jon Hunter
    Signed-off-by: Vinod Koul

    Jon Hunter
     

11 Mar, 2016

1 commit

16 Nov, 2015

1 commit

24 Sep, 2015

1 commit

  • 9ab8b4e7c   dmaengine: idma: rename to INTEL_IDMA64 ... Browse Code »

    the symbol CONFIG_IDMA64 should rather be CONFIG_INTEL_IDMA64 to conform to
    rest of the intel dmaengine drivers. This was found after sorting the
    entries and trying to place this odd one

    Suggested-by: Linus Torvalds
    Acked-by: Andy Shevchenko
    Signed-off-by: Vinod Koul

    Vinod Koul