02 Dec, 2020
1 commit
-
Because dfl.c uses the 'devm_ioremap', 'devm_iounmap',
'devm_ioremap_resource', and 'devm_platform_ioremap_resource'
functions, it should depend on HAS_IOMEM.This fixes make allyesconfig under UML (ARCH=um), which doesn't provide
HAS_IOMEM.[mdf@kernel.org: Removed "drivers: " in commit message]
Fixes: 89eb35e810a8 ("fpga: dfl: map feature mmio resources in their own feature drivers")
Signed-off-by: David Gow
Signed-off-by: Moritz Fischer
Link: https://lore.kernel.org/r/20201122001549.107023-2-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman
10 Sep, 2020
1 commit
-
A new bus type "dfl" is introduced for private features which are not
initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these
private features could be handled by separate driver modules.DFL feature drivers (dfl-fme, dfl-port) will create DFL devices on
enumeration. DFL drivers could be registered on this bus to match these
DFL devices. They are matched by dfl type & feature_id.[mdf@kernel.org: Add missing Documentation part to MAINTAINERS file]
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Signed-off-by: Matthew Gerlach
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
05 Sep, 2020
1 commit
-
Clean up an outdated comment claiming FPGA regions implement devicetree
support for reprogramming FPGAs.Signed-off-by: Moritz Fischer
31 Aug, 2020
5 commits
-
This patch makes preparation for modularization of DFL sub feature
drivers.DFL based FPGA devices may contain some IP blocks which are already
supported by kernel, most of them are supported by platform device
drivers. We could create platform devices for these IP blocks and get them
supported by these drivers.An important issue is that platform device drivers usually requests mmio
resources on probe. But now DFL mmio is mapped in DFL bus driver (e.g.
dfl-pci) as a whole region. Then platform device drivers for sub features
can't request their own mmio resources again. This is what the patch
trying to resolve.This patch changes the DFL enumeration. DFL bus driver will unmap mmio
resources after first step enumeration and pass enumeration info to DFL
framework. Then DFL framework will map the mmio resources again, do 2nd
step enumeration, and also unmap the mmio resources. In this way, sub
feature drivers could then request their own mmio resources as needed.An exception is that mmio resource of FIU headers are still mapped in DFL
bus driver. The FIU headers have some fundamental functions (sriov set,
port enable/disable) needed for DFL bus devices and other sub features.
They should not be unmapped as long as DFL bus device is alive.Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Signed-off-by: Matthew Gerlach
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer -
When the DONE pin does not go high after programming to confirm programming
success, the INIT_B pin provides some info on the reason. Use it if
available to provide a more explanatory error message.Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
Signed-off-by: Moritz Fischer -
Current code calls gpiod_get_value() without error checking. Should the
GPIO controller fail, execution would continue without any error message.Fix by checking for negative error values.
Reported-by: Tom Rix
Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
Signed-off-by: Moritz Fischer -
If this routine sleeps because it was scheduled out, it might miss DONE
going asserted and consider it a timeout. This would potentially make the
code return an error even when programming succeeded. Rewrite the loop to
always check DONE after checking if timeout expired so this cannot happen
anymore.While there, also add error checking for gpiod_get_value(). Also avoid
checking the DONE GPIO in two places, which would make the error-checking
code duplicated and more annoying.The new loop it written to still guarantee that we apply 8 extra CCLK
cycles after DONE has gone asserted, which is required by the hardware.Reported-by: Tom Rix
Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
Signed-off-by: Moritz Fischer -
Most dev_err messages in this file have no final dot. Remove the only two
exceptions to make them consistent.Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
Signed-off-by: Moritz Fischer
20 Aug, 2020
3 commits
-
Remove comment committed by mistake.
Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during write_init")
Signed-off-by: Luca Ceresoli
Signed-off-by: Moritz Fischer -
The feature id is stored in a 12 bit field in DFH. So a u16 variable is
enough for feature id.This patch changes all feature id related places to fit u16.
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer -
When CTRL+C occurs during the process of FPGA reconfiguration, the FPGA
reconfiguration process stops and the user can't perform a new FPGA
reconfiguration properly.Set FPGA task to be not interruptible so that the user can properly
perform FPGA reconfiguration after CTRL+C event.Signed-off-by: Richard Gong
Reviewed-by: Tom Rix
Signed-off-by: Moritz Fischer
27 Jul, 2020
1 commit
-
This should resolve the merge/build issues reported when trying to
create linux-next.Reported-by: Stephen Rothwell
Signed-off-by: Greg Kroah-Hartman
23 Jul, 2020
1 commit
-
…nux-fpga into char-misc-next
Moritz writes:
FPGA Manager changes for 5.9-rc1
Here is the (slightly larger than usual) patch set for the 5.9-rc1 merge
window.DFL:
- Xu's changes add support for AFU interrupt handling and puts them to
use for error handling.
- Xu's other change also adds another device-id for the Intel FPGA PAC N3000.
- John's change converts from using get_user_pages() to
pin_user_pages().
- Gustavo's patch cleans up some of the allocation by using
struct_size().Xilinx:
- Luca's changes clean up the xilinx-spi and xilinx-slave-serial drivers
and updates the comments and dt-bindings to reflect the fact it also
supports 7 series devices.Core:
- Tom cleaned up the fpga-bridge / fpga-mgr core by removing some
dead-stores.All patches have been reviewed on the mailing list, and have been in the
last few linux-next releases (as part of my for-next branch) without issues.Signed-off-by: Moritz Fischer <mdf@kernel.org>
* tag 'fpga-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
fpga: dfl: pci: add device id for Intel FPGA PAC N3000
Documentation: fpga: dfl: add descriptions for interrupt related interfaces.
fpga: dfl: afu: add AFU interrupt support
fpga: dfl: fme: add interrupt support for global error reporting
fpga: dfl: afu: add interrupt support for port error reporting
fpga: dfl: introduce interrupt trigger setting API
fpga: dfl: pci: add irq info for feature devices enumeration
fpga: dfl: parse interrupt info for feature devices on enumeration
fpga manager: xilinx-spi: check INIT_B pin during write_init
dt-bindings: fpga: xilinx-slave-serial: add optional INIT_B GPIO
fpga: Fix dead store in fpga-bridge.c
fpga: Fix dead store fpga-mgr.c
fpga: dfl: Use struct_size() in kzalloc()
fpga manager: xilinx-spi: remove unneeded, mistyped variables
fpga manager: xilinx-spi: valid for the 7 Series too
dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too
fpga: dfl: afu: convert get_user_pages() --> pin_user_pages()
14 Jul, 2020
2 commits
-
When putting the port in reset, driver must wait for the soft reset
acknowledgment bit instead of the soft reset bit.Fixes: 47c1b19c160f (fpga: dfl: afu: add port ops support)
Signed-off-by: Matthew Gerlach
Signed-off-by: Xu Yilun
Acked-by: Wu Hao
Reviewed-by: Tom Rix
Signed-off-by: Moritz Fischer -
This is to fix lkp cppcheck warnings:
drivers/fpga/dfl-pci.c:230:6: warning: The scope of the variable 'ret' can be reduced. [variableScope]
int ret = 0;
^drivers/fpga/dfl-pci.c:230:10: warning: Variable 'ret' is assigned a value that is never used. [unreadVariable]
int ret = 0;
^Fixes: 3c2760b78f90 ("fpga: dfl: pci: fix return value of cci_pci_sriov_configure")
Reported-by: kbuild test robot
Signed-off-by: Xu Yilun
Acked-by: Wu Hao
Reviewed-by: Tom Rix
Signed-off-by: Moritz Fischer
13 Jul, 2020
1 commit
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Add PCIe Device ID for Intel FPGA PAC N3000.
Signed-off-by: Wu Hao
Signed-off-by: Xu Yilun
Signed-off-by: Matthew Gerlach
Signed-off-by: Russ Weight
Reviewed-by: Wu Hao
Reviewed-by: Tom Rix
Signed-off-by: Moritz Fischer
07 Jul, 2020
3 commits
-
AFU (Accelerated Function Unit) is dynamic region of the DFL based FPGA,
and always defined by users. Some DFL based FPGA cards allow users to
implement their own interrupts in AFU. In order to support this,
hardware implements a new UINT (AFU Interrupt) private feature with
related capability register which describes the number of supported
AFU interrupts as well as the local index of the interrupts for
software enumeration, and from software side, driver follows the common
DFL interrupt notification and handling mechanism, and it implements
two ioctls below for user to query number of irqs supported and set/unset
interrupt triggers.Ioctls:
* DFL_FPGA_PORT_UINT_GET_IRQ_NUM
get the number of irqs, which is used to determine how many interrupts
UINT feature supports.* DFL_FPGA_PORT_UINT_SET_IRQ
set/unset eventfds as AFU interrupt triggers.Signed-off-by: Luwei Kang
Signed-off-by: Wu Hao
Signed-off-by: Xu Yilun
Reviewed-by: Marcelo Tosatti
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer -
Error reporting interrupt is very useful to notify users that some
errors are detected by the hardware. Once users are notified, they
could query hardware logged error states, no need to continuously
poll on these states.This patch adds interrupt support for fme global error reporting sub
feature. It follows the common DFL interrupt notification and handling
mechanism. And it implements two ioctls below for user to query
number of irqs supported, and set/unset interrupt triggers.Ioctls:
* DFL_FPGA_FME_ERR_GET_IRQ_NUM
get the number of irqs, which is used to determine whether/how many
interrupts fme error reporting feature supports.* DFL_FPGA_FME_ERR_SET_IRQ
set/unset given eventfds as fme error reporting interrupt triggers.Signed-off-by: Luwei Kang
Signed-off-by: Wu Hao
Signed-off-by: Xu Yilun
Reviewed-by: Marcelo Tosatti
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer -
Error reporting interrupt is very useful to notify users that some
errors are detected by the hardware. Once users are notified, they
could query hardware logged error states, no need to continuously
poll on these states.This patch adds interrupt support for port error reporting sub feature.
It follows the common DFL interrupt notification and handling mechanism,
implements two ioctl commands below for user to query number of irqs
supported, and set/unset interrupt triggers.Ioctls:
* DFL_FPGA_PORT_ERR_GET_IRQ_NUM
get the number of irqs, which is used to determine whether/how many
interrupts error reporting feature supports.* DFL_FPGA_PORT_ERR_SET_IRQ
set/unset given eventfds as error interrupt triggers.Signed-off-by: Luwei Kang
Signed-off-by: Wu Hao
Signed-off-by: Xu Yilun
Reviewed-by: Marcelo Tosatti
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
29 Jun, 2020
3 commits
-
FPGA user applications may be interested in interrupts generated by
DFL features. For example, users can implement their own FPGA
logics with interrupts enabled in AFU (Accelerated Function Unit,
dynamic region of DFL based FPGA). So user applications need to be
notified to handle these interrupts.In order to allow userspace applications to monitor interrupts,
driver requires userspace to provide eventfds as interrupt
notification channels. Applications then poll/select on the eventfds
to get notified.This patch introduces a generic helper functions to do eventfds binding
with given interrupts.Sub feature drivers are expected to use XXX_GET_IRQ_NUM to query irq
info, and XXX_SET_IRQ to set eventfds for interrupts. This patch also
introduces helper functions for these 2 ioctls.Signed-off-by: Luwei Kang
Signed-off-by: Wu Hao
Signed-off-by: Xu Yilun
Signed-off-by: Tom Rix
Reviewed-by: Marcelo Tosatti
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer -
Some DFL FPGA PCIe cards (e.g. Intel FPGA Programmable Acceleration
Card) support MSI-X based interrupts. This patch allows PCIe driver
to prepare and pass interrupt resources to DFL via enumeration API.
These interrupt resources could then be assigned to actual features
which use them.Signed-off-by: Luwei Kang
Signed-off-by: Wu Hao
Signed-off-by: Xu Yilun
Signed-off-by: Tom Rix
Reviewed-by: Marcelo Tosatti
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer -
DFL based FPGA devices could support interrupts for different purposes,
but current DFL framework only supports feature device enumeration with
given MMIO resources information via common DFL headers. This patch
introduces one new API dfl_fpga_enum_info_add_irq for low level bus
drivers (e.g. PCIe device driver) to pass its interrupt resources
information to DFL framework for enumeration, and also adds interrupt
enumeration code in framework to parse and assign interrupt resources
for enumerated feature devices and their own sub features.With this patch, DFL framework enumerates interrupt resources for core
features, including PORT Error Reporting, FME (FPGA Management Engine)
Error Reporting and also AFU User Interrupts.Signed-off-by: Luwei Kang
Signed-off-by: Wu Hao
Signed-off-by: Xu Yilun
Reviewed-by: Marcelo Tosatti
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
27 Jun, 2020
1 commit
-
The INIT_B pin reports the status during startup and after the end of the
programming process. However the current driver completely ignores it.Check the pin status during startup to make sure programming is never
started too early and also to detect any hardware issues in the FPGA
connection.This is optional for backward compatibility. If INIT_B is not passed by
device tree, just fallback to the old udelays.Signed-off-by: Luca Ceresoli
Signed-off-by: Moritz Fischer
26 Jun, 2020
1 commit
-
…mdf/linux-fpga into char-misc-next
FPGA Manager fixes for 5.8-rc1
Here is one (late) fix for 5.8-rc1 merge window.
Arnd's change addresses a missing build dependency.
All patches have been reviewed on the mailing list, and have been in the
last few linux-next releases (as part of my fixes branch) without issues.Signed-off-by: Moritz Fischer <mdf@kernel.org>
* tag 'fpga-fixes-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
fpga: zynqmp: fix modular build
19 Jun, 2020
6 commits
-
Using clang's scan-build/view this issue was flagged
a dead store issue in fpga-bridge.cwarning: Value stored to 'ret' is never read [deadcode.DeadStores]
ret = id;Signed-off-by: Tom Rix
Signed-off-by: Moritz Fischer -
Using clang's scan-build/view this issue was flagged in fpga-mgr.c
drivers/fpga/fpga-mgr.c:585:3: warning: Value stored to 'ret' is never read [deadcode.DeadStores]
ret = id;Signed-off-by: Tom Rix
Signed-off-by: Moritz Fischer -
Make use of the struct_size() helper instead of an open-coded version
in order to avoid any potential type mistakes. Also, remove unnecessary
function dfl_feature_platform_data_size().This code was detected with the help of Coccinelle and, audited and
fixed manually.Signed-off-by: Gustavo A. R. Silva
Signed-off-by: Moritz Fischer -
Using variables does not add readability here: parameters passed
to udelay*() are obviously in microseconds and their meaning is clear
from the context.The type is also wrong, udelay expects an unsigned long.
Signed-off-by: Luca Ceresoli
Signed-off-by: Moritz Fischer -
The Xilinx 7-series uses the same protocol, mention that.
Signed-off-by: Luca Ceresoli
Signed-off-by: Moritz Fischer -
This code was using get_user_pages_fast(), in a "Case 2" scenario
(DMA/RDMA), using the categorization from [1]. That means that it's
time to convert the get_user_pages_fast() + put_page() calls to
pin_user_pages_fast() + unpin_user_pages() calls.There is some helpful background in [2]: basically, this is a small
part of fixing a long-standing disconnect between pinning pages, and
file systems' use of those pages.[1] Documentation/core-api/pin_user_pages.rst
[2] "Explicit pinning of user-space pages":
https://lwn.net/Articles/807108/Cc: Xu Yilun
Cc: Wu Hao
Cc: Moritz Fischer
Cc: linux-fpga@vger.kernel.org
Signed-off-by: John Hubbard
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
09 Jun, 2020
1 commit
-
Two symbols need to be exported to allow the zynqmp-fpga module
to get loaded dynamically:ERROR: modpost: "zynqmp_pm_fpga_load" [drivers/fpga/zynqmp-fpga.ko] undefined!
ERROR: modpost: "zynqmp_pm_fpga_get_status" [drivers/fpga/zynqmp-fpga.ko] undefined!To ensure this is done correctly, also fix the Kconfig dependency
to only allow building the fpga driver when the firmware driver is
either disabled, or when it is reachable. With that, the dependency
on the SoC itself can be removed, and there are no surprises when
the fpga driver is built-in but the firmware a module.Fixes: 4db8180ffe7c ("firmware: xilinx: Remove eemi ops for fpga related APIs")
Signed-off-by: Arnd Bergmann
Signed-off-by: Moritz Fischer
08 Jun, 2020
1 commit
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Pull char/misc driver updates from Greg KH:
"Here is the large set of char/misc driver patches for 5.8-rc1Included in here are:
- habanalabs driver updates, loads
- mhi bus driver updates
- extcon driver updates
- clk driver updates (approved by the clock maintainer)
- firmware driver updates
- fpga driver updates
- gnss driver updates
- coresight driver updates
- interconnect driver updates
- parport driver updates (it's still alive!)
- nvmem driver updates
- soundwire driver updates
- visorbus driver updates
- w1 driver updates
- various misc driver updates
In short, loads of different driver subsystem updates along with the
drivers as well.All have been in linux-next for a while with no reported issues"
* tag 'char-misc-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (233 commits)
habanalabs: correctly cast u64 to void*
habanalabs: initialize variable to default value
extcon: arizona: Fix runtime PM imbalance on error
extcon: max14577: Add proper dt-compatible strings
extcon: adc-jack: Fix an error handling path in 'adc_jack_probe()'
extcon: remove redundant assignment to variable idx
w1: omap-hdq: print dev_err if irq flags are not cleared
w1: omap-hdq: fix interrupt handling which did show spurious timeouts
w1: omap-hdq: fix return value to be -1 if there is a timeout
w1: omap-hdq: cleanup to add missing newline for some dev_dbg
/dev/mem: Revoke mappings when a driver claims the region
misc: xilinx-sdfec: convert get_user_pages() --> pin_user_pages()
misc: xilinx-sdfec: cleanup return value in xsdfec_table_write()
misc: xilinx-sdfec: improve get_user_pages_fast() error handling
nvmem: qfprom: remove incorrect write support
habanalabs: handle MMU cache invalidation timeout
habanalabs: don't allow hard reset with open processes
habanalabs: GAUDI does not support soft-reset
habanalabs: add print for soft reset due to event
habanalabs: improve MMU cache invalidation code
...
02 Jun, 2020
1 commit
-
Pull uaccess/access_ok updates from Al Viro:
"Removals of trivially pointless access_ok() calls.Note: the fiemap stuff was removed from the series, since they are
duplicates with part of ext4 series carried in Ted's tree"* 'uaccess.access_ok' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
vmci_host: get rid of pointless access_ok()
hfi1: get rid of pointless access_ok()
usb: get rid of pointless access_ok() calls
lpfc_debugfs: get rid of pointless access_ok()
efi_test: get rid of pointless access_ok()
drm_read(): get rid of pointless access_ok()
via-pmu: don't bother with access_ok()
drivers/crypto/ccp/sev-dev.c: get rid of pointless access_ok()
omapfb: get rid of pointless access_ok() calls
amifb: get rid of pointless access_ok() calls
drivers/fpga/dfl-afu-dma-region.c: get rid of pointless access_ok()
drivers/fpga/dfl-fme-pr.c: get rid of pointless access_ok()
cm4000_cs.c cmm_ioctl(): get rid of pointless access_ok()
nvram: drop useless access_ok()
n_hdlc_tty_read(): remove pointless access_ok()
tomoyo_write_control(): get rid of pointless access_ok()
btrfs_ioctl_send(): don't bother with access_ok()
fat_dir_ioctl(): hadn't needed that access_ok() for more than a decade...
dlmfs_file_write(): get rid of pointless access_ok()
29 May, 2020
2 commits
-
Address is passed to get_user_pages_fast(), which does access_ok().
NB: this is called only from ->ioctl(), and only under USER_DS.Signed-off-by: Al Viro
-
followed by copy_from_user()
Signed-off-by: Al Viro
19 May, 2020
1 commit
-
Corrected error handling goto sequnece. Level put_pages should
be called when pinned pages >= 0 && pinned != npages. Level
free_pages should be called when pinned pages < 0.Fixes: fa8dda1edef9 ("fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support")
Signed-off-by: Souptick Joarder
Acked-by: Wu Hao
Reviewed-by: Xu Yilun
Link: https://lore.kernel.org/r/1589825991-3545-1-git-send-email-jrdr.linux@gmail.com
Signed-off-by: Greg Kroah-Hartman
15 May, 2020
1 commit
-
…nux-fpga into char-misc-next
Moritz writes:
FPGA Manager changes for 5.8
Here's the first set of changes for the 5.8-rc1 merge window.
Dominic's change adds support for accessing AFU regions with gdb.
Gustavo's change is a cleanup patch regarding variable lenght arrays.
Richard's changes update dt-bindings and add support for stratix and agilex.
Sergiu's changes update spi transfers with the new delay field.
Xu's change addresses an issue with a wrong return value.
Shubhrajyoti's change makes the Zynq FPGA driver return -EPROBE_DEFER on
check of devm_clk_get failure.
Xu's change for DFL enables multiple opens.All of these patches have been reviewed, have appropriate Acked-by's and
have been in the last few linux-next releases without issues.Signed-off-by: Moritz Fischer <mdf@kernel.org>
* tag 'fpga-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
fpga: dfl: afu: support debug access to memory-mapped afu regions
fpga: dfl.h: Replace zero-length array with flexible-array member
arm64: dts: agilex: correct service layer driver's compatible value
dt-bindings, firmware: add compatible value Intel Stratix10 service layer binding
fpga: stratix10-soc: add compatible property value for intel agilex
arm64: dts: agilex: correct FPGA manager driver's compatible value
dt-bindings: fpga: add compatible value to Stratix10 SoC FPGA manager binding
fpga: machxo2-spi: Use new structure for SPI transfer delays
fpga: ice40-spi: Use new structure for SPI transfer delays
fpga: dfl: support multiple opens on feature device node.
30 Apr, 2020
3 commits
-
Allow debug access to memory-mapped regions using e.g. gdb.
Signed-off-by: Dominic Chen
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer -
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to declare
variable-length types such as these ones is a flexible array member[1][2],
introduced in C99:struct foo {
int stuff;
struct boo array[];
};By making use of the mechanism above, we will get a compiler warning
in case the flexible array does not occur last in the structure, which
will help us prevent some kind of undefined behavior bugs from being
inadvertently introduced[3] to the codebase from now on.Also, notice that, dynamic memory allocations won't be affected by
this change:"Flexible array members have incomplete type, and so the sizeof operator
may not be applied. As a quirk of the original implementation of
zero-length arrays, sizeof evaluates to zero."[1]This issue was found with the help of Coccinelle.
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
[2] https://github.com/KSPP/linux/issues/21
[3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")Signed-off-by: Gustavo A. R. Silva
Signed-off-by: Moritz Fischer -
Add compatible property value so we can reuse FPGA manager driver on
Intel Agilex SoC platform.Signed-off-by: Richard Gong
Signed-off-by: Moritz Fischer
