Eric Lee / smarc-fsl-linux-kernel

08 Nov, 2019

1 commit

  • 606397d67   fsi: Add ast2600 master driver ... Browse Code »

    The ast2600 BMC has a pair of FSI masters in it, behind an AHB to OPB
    bridge.

    The master driver supports reads and writes of full words, half word and
    byte accesses to remote CFAMs. It can perform very basic error recovery
    through resetting of the FSI port when an error is detected, and the
    issuing of breaks and terms.

    Signed-off-by: Joel Stanley
    Acked-by: Alistair Popple
    --
    v2:
    - remove debugging
    - squash in fixes
    Link: https://lore.kernel.org/r/20191108051945.7109-10-joel@jms.id.au
    Signed-off-by: Greg Kroah-Hartman

    Joel Stanley
     

21 May, 2019

1 commit

03 Dec, 2018

1 commit

  • 7ed98dddb   fsi: Add On-Chip Controller (OCC) driver ... Browse Code »

    The OCC is a device embedded on a POWER processor that collects and
    aggregates sensor data from the processor and system. The OCC can
    provide the raw sensor data as well as perform thermal and power
    management on the system.

    This driver provides an atomic communications channel between a service
    processor (e.g. a BMC) and the OCC. The driver is dependent on the FSI
    SBEFIFO driver to get hardware access through the SBE to the OCC SRAM.
    Commands are issued to the SBE to send or fetch data to the SRAM.

    Signed-off-by: Eddie James
    Signed-off-by: Andrew Jeffery
    Signed-off-by: Benjamin Herrenschmidt
    Signed-off-by: Joel Stanley
    Signed-off-by: Guenter Roeck

    Eddie James
     

23 Jul, 2018

1 commit

  • 6a794a27d   fsi: master-ast-cf: Add new FSI master using Aspeed ColdFire ... Browse Code »

    The Aspeed AST2x00 can contain a ColdFire v1 coprocessor which
    is currently unused on OpenPower systems.

    This adds an alternative to the fsi-master-gpio driver that
    uses that coprocessor instead of bit banging from the ARM
    core itself. The end result is about 4 times faster.

    The firmware for the coprocessor and its source code can be
    found at https://github.com/ozbenh/cf-fsi and is system specific.

    Signed-off-by: Benjamin Herrenschmidt

    Benjamin Herrenschmidt
     

12 Jun, 2018

1 commit

  • 9f4a8a2d7   fsi/sbefifo: Add driver for the SBE FIFO ... Browse Code »

    This driver provides an in-kernel and a user API for accessing
    the command FIFO of the SBE (Self Boot Engine) of the POWER9
    processor, via the FSI bus.

    It provides an in-kernel interface to submit command and receive
    responses, along with a helper to locate and analyse the response
    status block. It's a simple synchronous submit() type API.

    The user interface uses the write/read interface that an earlier
    version of this driver already provided, however it has some
    specific limitations in order to keep the driver simple and
    avoid using up a lot of kernel memory:

    - The user should perform a single write() with the command and
    a single read() to get the response (with a buffer big enough
    to hold the entire response).

    - On a write() the command is simply "stored" into a kernel buffer,
    it is submitted as one operation on the subsequent read(). This
    allows to have the code write directly from the FIFO into the user
    buffer and avoid hogging the SBE between the write() and read()
    syscall as it's critical that the SBE be freed asap to respond
    to the host. An extra write() will simply replace the previously
    written command.

    - A write of a single 4 bytes containing the value 0x52534554
    in big endian will trigger a reset request. No read is necessary,
    the write() call will return when the reset has been acknowledged
    or times out.

    - The command is limited to 4K bytes.

    Signed-off-by: Benjamin Herrenschmidt
    Tested-by: Joel Stanley
    ---

    Benjamin Herrenschmidt
     

09 Jun, 2017

3 commits

  • 7f9e8f767   drivers/fsi: Add hub master support ... Browse Code »

    Add an engine driver to expose a "hub" FSI master - which has a set of
    control registers in the engine address space, and uses a chunk of the
    slave address space for actual FSI communication.

    Additional changes from Jeremy Kerr .

    Signed-off-by: Christopher Bostic
    Signed-off-by: Jeremy Kerr
    Signed-off-by: Joel Stanley
    Signed-off-by: Greg Kroah-Hartman

    Christopher Bostic
     
  • 680ca6dcf   drivers/fsi: Add SCOM FSI client device driver ... Browse Code »

    Create a simple SCOM engine device driver that reads and writes
    its control registers via an FSI bus.

    Includes changes from Edward A. James .

    Signed-off-by: Christopher Bostic
    Signed-off-by: Joel Stanley
    Signed-off-by: Edward A. James
    Signed-off-by: Jeremy Kerr
    Signed-off-by: Greg Kroah-Hartman

    Christopher Bostic
     
  • ac0385d9f   drivers/fsi: Add GPIO based FSI master ... Browse Code »

    Implement a FSI master using GPIO. Will generate FSI protocol for
    read and write commands to particular addresses. Sends master command
    and waits for and decodes a slave response.

    Includes changes from Edward A. James and Jeremy
    Kerr .

    Signed-off-by: Edward A. James
    Signed-off-by: Jeremy Kerr
    Signed-off-by: Christopher Bostic
    Signed-off-by: Joel Stanley
    Signed-off-by: Greg Kroah-Hartman

    Christopher Bostic
     

10 Feb, 2017

1 commit