25 Oct, 2020
1 commit
-
Pull ARM SoC platform updates from Olof Johansson:
"SoC changes, a substantial part of this is cleanup of some of the
older platforms that used to have a bunch of board files.In particular:
- Remove non-DT i.MX platforms that haven't seen activity in years,
it's time to remove them.- A bunch of cleanup and removal of platform data for TI/OMAP
platforms, moving over to genpd for power/reset control (yay!)- Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
closer to multiplatform support (not quite there yet, but getting
close).There are a few other changes too, smaller fixlets, etc. For new
platform support, the primary ones are:- New SoC: Hisilicon SD5203, ARM926EJ-S platform.
- Cpufreq support for i.MX7ULP"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits)
ARM: mstar: Select MStar intc
ARM: stm32: Replace HTTP links with HTTPS ones
ARM: debug: add UART early console support for SD5203
ARM: hisi: add support for SD5203 SoC
ARM: omap3: enable off mode automatically
clk: imx: imx35: Remove mx35_clocks_init()
clk: imx: imx31: Remove mx31_clocks_init()
clk: imx: imx27: Remove mx27_clocks_init()
ARM: imx: Remove unused definitions
ARM: imx35: Retrieve the IIM base address from devicetree
ARM: imx3: Retrieve the AVIC base address from devicetree
ARM: imx3: Retrieve the CCM base address from devicetree
ARM: imx31: Retrieve the IIM base address from devicetree
ARM: imx27: Retrieve the CCM base address from devicetree
ARM: imx27: Retrieve the SYSCTRL base address from devicetree
ARM: s3c64xx: bring back notes from removed debug-macro.S
ARM: s3c24xx: fix Wunused-variable warning on !MMU
ARM: samsung: fix PM debug build with DEBUG_LL but !MMU
MAINTAINERS: mark linux-samsung-soc list non-moderated
ARM: imx: Remove remnant board file support pieces
...
15 Oct, 2020
1 commit
-
Pull MFD updates from Lee Jones:
"New Drivers:
- Add support for initialising shared (between children) Regmaps
- Add support for Kontron SL28CPLD
- Add support for ENE KB3930 Embedded Controller
- Add support for Intel FPGA PAC MAX 10 BMCNew Device Support:
- Add support for Power to Ricoh RN5T618
- Add support for UART to Intel Lakefield
- Add support for LP87524_Q1 to Texas Instruments LP87565New Functionality:
- Device Tree; ene-kb3930, sl28cpld, syscon, lp87565, lp87524-q1
- Use new helper dev_err_probe(); madera-core, stmfx, wcd934x
- Use new GPIOD API; dm355evm_msp
- Add wake-up capability; sprd-sc27xx-spi
- Add ACPI support; kempld-coreFix-ups:
- Trivial (spelling/whitespace); Kconfig, ab8500
- Fix for unused variables; khadas-mcu, kempld-core
- Remove unused header file(s); mt6360-core
- Use correct IRQ flags in docs; act8945a, gateworks-gsc, rohm,bd70528-pmic
- Add COMPILE_TEST support; asic3, tmio_core
- Add dependency on I2C; SL28CPLDBug Fixes:
- Fix memory leak(s); sm501
- Do not free regmap_config's 'name' until exit; syscon"* tag 'mfd-next-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (34 commits)
mfd: kempld-core: Fix unused variable 'kempld_acpi_table' when !ACPI
mfd: sl28cpld: Depend on I2C
mfd: asic3: Build if COMPILE_TEST=y
dt-bindings: mfd: Correct interrupt flags in examples
mfd: Add ACPI support to Kontron PLD driver
mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC
mfd: lp87565: Add LP87524-Q1 variant
dt-bindings: mfd: Add LP87524-Q1
dt-bindings: mfd: lp87565: Convert to yaml
mfd: mt6360: Remove unused include
mfd: sm501: Fix leaks in probe()
mfd: syscon: Don't free allocated name for regmap_config
dt-bindings: mfd: syscon: Document Exynos3 and Exynos5433 compatibles
dt-bindings: mfd: syscon: Merge Samsung Exynos Sysreg bindings
dt-bindings: mfd: ab8500: Remove weird Unicode characters
mfd: sprd: Add wakeup capability for PMIC IRQ
mfd: intel-lpss: Add device IDs for UART ports for Lakefield
mfd: dm355evm_msp: Convert LEDs to GPIO descriptor table
mfd: wcd934x: Simplify with dev_err_probe()
mfd: stmfx: Simplify with dev_err_probe()
...
10 Oct, 2020
2 commits
-
Signed-off-by: Marc Zyngier
-
Add MStar interrupt controller support using hierarchy irq
domain.Signed-off-by: Mark-PK Tsai
Signed-off-by: Marc Zyngier
Tested-by: Daniel Palmer
Link: https://lore.kernel.org/r/20200902063344.1852-2-mark-pk.tsai@mediatek.com
28 Sep, 2020
1 commit
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…gin/irq/owl' into irq/irqchip-next
Signed-off-by: Marc Zyngier <maz@kernel.org>
25 Sep, 2020
1 commit
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This interrupt controller is found in the Actions Semi Owl SoCs (S500,
S700 and S900) and provides support for handling up to 3 external
interrupt lines.Each line can be independently configured as interrupt and triggers on
either of the edges or either of the levels. Additionally, each line
can also be masked individually.Co-developed-by: Parthiban Nallathambi
Co-developed-by: Saravanan Sekar
Signed-off-by: Parthiban Nallathambi
Signed-off-by: Saravanan Sekar
Signed-off-by: Cristian Ciocaltea
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/1a010ef0eb78831b5657d74a0fcdef7a8efb2ec4.1600114378.git.cristian.ciocaltea@gmail.com
17 Sep, 2020
2 commits
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Add support for the interrupt controller inside the sl28 CPLD management
controller.The interrupt controller can handle at most 8 interrupts and is really
simplistic and consists only of an interrupt mask and an interrupt
pending register.Signed-off-by: Michael Walle
Acked-by: Marc Zyngier
Signed-off-by: Lee Jones -
The Programmable Real-Time Unit Subsystem (PRUSS) contains a local
interrupt controller (INTC) that can handle various system input events
and post interrupts back to the device-level initiators. The INTC can
support upto 64 input events with individual control configuration and
hardware prioritization. These events are mapped onto 10 output interrupt
lines through two levels of many-to-one mapping support. Different
interrupt lines are routed to the individual PRU cores or to the host
CPU, or to other devices on the SoC. Some of these events are sourced
from peripherals or other sub-modules within that PRUSS, while a few
others are sourced from SoC-level peripherals/devices.The PRUSS INTC platform driver manages this PRUSS interrupt controller
and implements an irqchip driver to provide a Linux standard way for
the PRU client users to enable/disable/ack/re-trigger a PRUSS system
event. The system events to interrupt channels and output interrupts
relies on the mapping configuration provided either through the PRU
firmware blob (for interrupts routed to PRU cores) or via the PRU
application's device tree node (for interrupt routed to the main CPU).
In the first case the mappings will be programmed on PRU remoteproc
driver demand (via irq_create_fwspec_mapping) during the boot of a PRU
core and cleaned up after the PRU core is stopped.Reference counting is used to allow multiple system events to share a
single channel and to allow multiple channels to share a single host
event.The PRUSS INTC module is reference counted during the interrupt
setup phase through the irqchip's irq_request_resources() and
irq_release_resources() ops. This restricts the module from being
removed as long as there are active interrupt users.The driver currently supports and can be built for OMAP architecture
based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based
66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs.
All of these SoCs support 64 system events, 10 interrupt channels and
10 output interrupt lines per PRUSS INTC with a few SoC integration
differences.NOTE:
Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that
enables multiple external events to be routed to a specific number
of input interrupt events. Any non-default external interrupt event
directed towards PRUSS needs this crossbar to be setup properly.Co-developed-by: Suman Anna
Co-developed-by: Andrew F. Davis
Co-developed-by: Roger Quadros
Co-developed-by: David Lechner
Signed-off-by: Suman Anna
Signed-off-by: Andrew F. Davis
Signed-off-by: Roger Quadros
Signed-off-by: David Lechner
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Marc Zyngier
20 Aug, 2020
1 commit
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It was a good idea to move it out at first, but the irqchip code
is still tightly connected to the s3c24xx platform code and uses
multiple internal header files, so just move it back for the
time being to avoid those dependencies.Signed-off-by: Arnd Bergmann
Acked-by: Marc Zyngier
Link: https://lore.kernel.org/r/20200806182059.2431-21-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski
10 Jun, 2020
1 commit
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The RISC-V per-HART local interrupt controller manages software
interrupts, timer interrupts, external interrupts (which are routed
via the platform level interrupt controller) and other per-HART
local interrupts.We add a driver for the RISC-V local interrupt controller, which
eventually replaces the RISC-V architecture code, allowing for a
better split between arch code and drivers.The driver is compliant with RISC-V Hart-Level Interrupt Controller
DT bindings located at:
Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txtCo-developed-by: Palmer Dabbelt
Signed-off-by: Anup Patel
[Palmer: Cleaned up warnings]
Signed-off-by: Palmer Dabbelt
29 May, 2020
3 commits
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This controller appears on Loongson LS7A family of PCH to transform
interrupts from PCI MSI into HyperTransport vectorized interrrupts
and send them to procrssor's HT vector controller.Signed-off-by: Jiaxun Yang
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20200528152757.1028711-6-jiaxun.yang@flygoat.com -
This controller appears on Loongson LS7A family of PCH to transform
interrupts from devices into HyperTransport vectorized interrrupts
and send them to procrssor's HT vector controller.Signed-off-by: Jiaxun Yang
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20200528152757.1028711-4-jiaxun.yang@flygoat.com -
This controller appears on Loongson-3 chips for receiving interrupt
vectors from PCH's PIC and PCH's PCIe MSI interrupts.Signed-off-by: Jiaxun Yang
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20200528152757.1028711-2-jiaxun.yang@flygoat.com
25 Mar, 2020
2 commits
-
This controller appeared on Loongson-3 family of chips to receive
interrupts from PCH PIC.
It is a I8259 with optimized interrupt polling flow. We can poll
interrupt number from HT vector directly but still have to follow
standard I8259 routines to mask, unmask and EOI.Signed-off-by: Jiaxun Yang
Co-developed-by: Huacai Chen
Signed-off-by: Huacai Chen
Reviewed-by: Marc Zyngier
Signed-off-by: Thomas Bogendoerfer -
This controller appeared on Loongson family of chips as the primary
package interrupt source.Signed-off-by: Jiaxun Yang
Co-developed-by: Huacai Chen
Signed-off-by: Huacai Chen
Reviewed-by: Marc Zyngier
Signed-off-by: Thomas Bogendoerfer
21 Jan, 2020
3 commits
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The Interrupt Multiplexer (INTMUX) expands the number of peripherals
that can interrupt the core:
* The INTMUX has 8 channels that are assigned to 8 NVIC interrupt slots.
* Each INTMUX channel can receive up to 32 interrupt sources and has 1
interrupt output.
* The INTMUX routes the interrupt sources to the interrupt outputs.Signed-off-by: Shengjiu Wang
Signed-off-by: Joakim Zhang
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20200117060653.27485-3-qiangqing.zhang@nxp.com -
This patch is written to clean up dependency of ARCH_EXYNOS
Not all exynos device have IRQ_COMBINER, especially aarch64 EXYNOS
but it is built for all exynos devices.
Thus add the config for EXYNOS_IRQ_COMBINER
remove direct dependency between ARCH_EXYNOS and exynos-combiner.c
and only selected on the aarch32 devicesSigned-off-by: Hyunki Koo
Signed-off-by: Marc Zyngier
Reviewed-by: Krzysztof Kozlowski
Link: https://lore.kernel.org/r/20191224211108.7128-1-hyunki00.koo@gmail.com -
The Aspeed SOCs provide some interrupts through the System Control
Unit registers. Add an interrupt controller that provides these
interrupts to the system.Signed-off-by: Eddie James
Signed-off-by: Marc Zyngier
Reviewed-by: Andrew Jeffery
Link: https://lore.kernel.org/r/1579123790-6894-3-git-send-email-eajames@linux.ibm.com
11 Nov, 2019
1 commit
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The LS1021A allows inverting the polarity of six interrupt lines
IRQ[0:5] via the scfg_intpcr register, effectively allowing
IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
check the type, set the relevant bit in INTPCR accordingly, and fixup
the type argument before calling the GIC's irq_set_type.In fact, the power-on-reset value of the INTPCR register on the LS1021A
is so that all six lines have their polarity inverted. Hence any
hardware connected to those lines is unusable without this: If the line
is indeed active low, the generic GIC code will reject an irq spec with
IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously
disable the polarity inversion (writing 0 to the relevant bit) before
unmasking the interrupt.Some other Layerscape SOCs (LS1043A, LS1046A) have a similar feature,
just with a different number of external interrupt lines (and a
different POR value for the INTPCR register). This driver should be
prepared for supporting those by properly filling out the device tree
node. I have the reference manuals for all three boards, but I've only
tested the driver on an LS1021A.Unfortunately, the Kconfig symbol ARCH_LAYERSCAPE only exists on
arm64, so do as is done for irq-ls-scfg-msi.c: introduce a new symbol
which is set when either ARCH_LAYERSCAPE or SOC_LS1021A is set.Signed-off-by: Rasmus Villemoes
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20191107122115.6244-3-linux@rasmusvillemoes.dk
09 Aug, 2019
1 commit
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This driver handles the interrupt controller built in the Timer/Counter
Unit (TCU) of the JZ47xx SoCs from Ingenic.Signed-off-by: Paul Cercueil
Tested-by: Mathieu Malaterre
Tested-by: Artur Rojek
Reviewed-by: Thomas Gleixner
Acked-by: Marc Zyngier
Signed-off-by: Paul Burton
Cc: Ralf Baechle
Cc: James Hogan
Cc: Jonathan Corbet
Cc: Lee Jones
Cc: Arnd Bergmann
Cc: Daniel Lezcano
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: od@zcrc.me
03 Jul, 2019
1 commit
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The Amazon's Annapurna Labs Fabric Interrupt Controller has 32 inputs.
A FIC (Fabric Interrupt Controller) may be cascaded into another FIC or
directly to the main CPU Interrupt Controller (e.g. GIC).Signed-off-by: Talel Shenhar
Signed-off-by: Marc Zyngier
29 May, 2019
1 commit
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Add a driver for the Renesas RZ/A1 Interrupt Controller.
This supports using up to 8 external interrupts on RZ/A1, with
configurable sense select.NMI edge select is not yet supported.
Signed-off-by: Geert Uytterhoeven
Tested-by: Chris Brandt
Reviewed-by: Simon Horman
Signed-off-by: Marc Zyngier
20 May, 2019
1 commit
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Pull IRQ chip updates from Ingo Molnar:
"A late irqchips update:- New TI INTR/INTA set of drivers
- Rewrite of the stm32mp1-exti driver as a platform driver
- Update the IOMMU MSI mapping API to be RT friendly
- A number of cleanups and other low impact fixes"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits)
iommu/dma-iommu: Remove iommu_dma_map_msi_msg()
irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg()
irqchip/ls-scfg-msi: Don't map the MSI page in ls_scfg_msi_compose_msg()
irqchip/gic-v3-its: Don't map the MSI page in its_irq_compose_msi_msg()
irqchip/gicv2m: Don't map the MSI page in gicv2m_compose_msi_msg()
iommu/dma-iommu: Split iommu_dma_map_msi_msg() in two parts
genirq/msi: Add a new field in msi_desc to store an IOMMU cookie
arm64: arch_k3: Enable interrupt controller drivers
irqchip/ti-sci-inta: Add msi domain support
soc: ti: Add MSI domain bus support for Interrupt Aggregator
irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver
dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings
irqchip/ti-sci-intr: Add support for Interrupt Router driver
dt-bindings: irqchip: Introduce TISCI Interrupt router bindings
gpio: thunderx: Use the default parent apis for {request,release}_resources
genirq: Introduce irq_chip_{request,release}_resource_parent() apis
firmware: ti_sci: Add helper apis to manage resources
firmware: ti_sci: Add RM mapping table for am654
firmware: ti_sci: Add support for IRQ management
firmware: ti_sci: Add support for RM core ops
...
01 May, 2019
2 commits
-
Texas Instruments' K3 generation SoCs has an IP Interrupt Aggregator
which is an interrupt controller that does the following:
- Converts events to interrupts that can be understood by
an interrupt router.
- Allows for multiplexing of events to interrupts.Configuration of the interrupt aggregator registers can only be done by
a system co-processor and the driver needs to send a message to this
co processor over TISCI protocol. Add the required infrastructure to
allow the allocation and routing of these events.Signed-off-by: Lokesh Vutla
Signed-off-by: Marc Zyngier -
Texas Instruments' K3 generation SoCs has an IP Interrupt Router
that does allows for redirection of input interrupts to host
interrupt controller. Interrupt Router inputs are either from a
peripheral or from an Interrupt Aggregator which is another
interrupt controller.Configuration of the interrupt router registers can only be done by
a system co-processor and the driver needs to send a message to this
co processor over TISCI protocol.Add support for Interrupt Router driver over TISCI protocol.
Signed-off-by: Lokesh Vutla
Signed-off-by: Marc Zyngier
20 Apr, 2019
1 commit
-
The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale
platform that has very wide deployment and use.As part of modernizing the platform, we need to implement a
proper irqchip in the irqchip subsystem.The IXP4xx irqchip is tightly jotted together with the GPIO
controller, and whereas in the past we would deal with this
complex logic by adding necessarily different code, we can
nowadays modernize it using a hierarchical irqchip.The actual IXP4 irqchip is a simple active low level IRQ
controller, whereas the GPIO functionality resides in a
different memory area and adds edge trigger support for
the interrupts.The interrupts from GPIO lines 0..12 are 1:1 mapped to
a fixed set of hardware IRQs on this IRQchip, so we
expect the child GPIO interrupt controller to go in and
allocate descriptors for these interrupts.For the other interrupts, as we do not yet have DT
support for this platform, we create a linear irqdomain
and then go in and allocate the IRQs that the legacy
boards use. This code will be removed on the DT probe
path when we add DT support to the platform.We add some translation code for supporting DT
translations for the fwnodes, but we leave most of that
for later.Cc: Marc Zyngier
Cc: Jason Cooper
Acked-by: Marc Zyngier
Signed-off-by: Linus Walleij
07 Mar, 2019
1 commit
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Pull ARM SoC late updates from Arnd Bergmann:
"Here are two branches that came relatively late during the linux-5.0
development cycle and have dependencies on the other branches:- On the TI OMAP platform, the CPSW Ethernet PHY mode selection
driver is being replaced, this puts the final pieces in place- On the DaVinci platform, the interrupt handling code in arch/arm
gets moved into a regular device driver in drivers/irqchip.Since they both had some time in linux-next after the 5.0-rc8 release,
I'm sending them along with the other updates"* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
net: ethernet: ti: cpsw: deprecate cpsw-phy-sel driver
ARM: davinci: remove intc related fields from davinci_soc_info
irqchip: davinci-cp-intc: move the driver to drivers/irqchip
ARM: davinci: cp-intc: remove redundant comments
ARM: davinci: cp-intc: drop GPL license boilerplate
ARM: davinci: cp-intc: use readl/writel_relaxed()
ARM: davinci: cp-intc: unify error handling
ARM: davinci: cp-intc: improve coding style
ARM: davinci: cp-intc: request the memory region before remapping it
ARM: davinci: cp-intc: use the new-style config structure
ARM: davinci: cp-intc: convert all hex numbers to lowercase
ARM: davinci: cp-intc: use a common prefix for all symbols
ARM: davinci: cp-intc: add the new config structures for da8xx SoCs
irqchip: davinci-cp-intc: add a new config structure
ARM: davinci: cp-intc: add a wrapper around cp_intc_init()
ARM: davinci: cp-intc: remove cp_intc.h
irqchip: davinci-aintc: move the driver to drivers/irqchip
ARM: davinci: aintc: remove unnecessary includes
ARM: davinci: aintc: remove the timer-specific irq_set_handler()
ARM: davinci: aintc: request memory region before remapping it
...
19 Feb, 2019
2 commits
-
The cp-intc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs.Acked-by: Marc Zyngier
Signed-off-by: Bartosz Golaszewski
Reviewed-by: David Lechner
Signed-off-by: Sekhar Nori -
The aintc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs. There's no device-tree support for any dm* board so
there's no IRQCHIP_OF_DECLARE() - there's only the exported init
function called from machine code.Acked-by: Marc Zyngier
Reviewed-by: David Lechner
Signed-off-by: Bartosz Golaszewski
Signed-off-by: Sekhar Nori
14 Feb, 2019
1 commit
-
This controller appeared on Loongson-1 family MCUs
including Loongson-1B and Loongson-1C.Signed-off-by: Jiaxun Yang
Signed-off-by: Marc Zyngier
18 Dec, 2018
2 commits
-
The irqsteer block is a interrupt multiplexer/remapper found on the
i.MX8 line of SoCs.Signed-off-by: Fugang Duan
Signed-off-by: Lucas Stach
Signed-off-by: Marc Zyngier -
The Cirrus Logic Madera codecs (Cirrus Logic CS47L35/85/90/91 and WM1840)
are highly complex devices containing up to 7 programmable DSPs and many
other internal sources of interrupts plus a number of GPIOs that can be
used as interrupt inputs. The large number (>150) of internal interrupt
sources are managed by an on-board interrupt controller.This driver provides the handling for the interrupt controller. As the
codec is accessed via regmap, we can make use of the generic IRQ
functionality from regmap to do most of the work. Only around half of
the possible interrupt source are currently of interest from the driver
so only this subset is defined. Others can be added in future if needed.The KConfig options are not user-configurable because this driver is
mandatory so is automatically included when the parent MFD driver is
selected.Signed-off-by: Richard Fitzgerald
Signed-off-by: Charles Keepax
Signed-off-by: Marc Zyngier
13 Dec, 2018
1 commit
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Add interrupt driver for RDA Micro RDA8810PL SoC.
Signed-off-by: Andreas Färber
Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Marc Zyngier
Signed-off-by: Marc Zyngier
29 Oct, 2018
1 commit
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Pull C-SKY architecture port from Guo Ren:
"This contains the Linux port for C-SKY(csky) based on linux-4.19
Release, which has been through 10 rounds of review on mailing list.More information:
http://en.c-sky.com
The development repo:
https://github.com/c-sky/csky-linux
ABI Documentation:
https://github.com/c-sky/csky-doc
Here is the pre-built cross compiler for fast test from our CI:
https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz
We use buildroot as our CI-test enviornment. "LTP, Lmbench ..." will
be tested for every commit. See here for more details:https://gitlab.com/c-sky/buildroot/pipelines
We'll continouslly improve csky subsystem in future"
Arnd acks, and adds the following notes:
"I did a thorough review of the ABI, which as usual mainly consists of
spotting any files that don't use the asm-generic ABI itself, and
having it changed to it matches exactly what we do on other new
architectures.I also looked at every other patch and commented on maybe half of them
where I saw something that did not quite seem right. Others have
reviewed specific patches in greater depth. I'm sure that one could
fine more of the minor details, but as long as they are not ABI
relevant, they can be fixed later.The only patch that is part of the ABI and that nobody reviewed is the
signal handling. This is one of the areas I never worked on in much
detail. I did not see anything wrong with it, but I also don't know
what the problems with the other architectures are here, and we seem
to be hitting issues occasionally, and we never managed to generalize
this enough for new architectures to have a trivial implementation.I was originally hoping that we could have the 64-bit time_t
interfaces ready in time to completely drop the 32-bit ones, but that
did not happen. We might still remove them in the next merge window
depending on whether the libc upstream people prefer to keep them or
not.One more general comment: I think this may well be the last new CPU
architecture we ever add to the kernel. Both nds32 and c-sky are made
by companies that also work on risc-v, and generally speaking risc-v
seems to be killing off any of the minor licensable instruction set
projects, just like ARM has mostly killed off the custom
vendor-specific instruction sets already.If we add another architecture in the future, it may instead be
something like the LLVM bitcode or WebAssembly, who knows?"To which Geert Uytterhoeven pipes in about another architecture still in
the pipeline: Kalray MPPA.* tag 'csky-for-linus-4.20' of https://github.com/c-sky/csky-linux: (24 commits)
dt-bindings: interrupt-controller: C-SKY APB intc
irqchip: add C-SKY APB bus interrupt controller
dt-bindings: interrupt-controller: C-SKY SMP intc
irqchip: add C-SKY SMP interrupt controller
MAINTAINERS: Add csky
dt-bindings: Add vendor prefix for csky
dt-bindings: csky CPU Bindings
csky: Misc headers
csky: SMP support
csky: Debug and Ptrace GDB
csky: User access
csky: Library functions
csky: ELF and module probe
csky: Atomic operations
csky: IRQ handling
csky: VDSO and rt_sigreturn
csky: Process management and Signal
csky: MMU and page table management
csky: Cache and TLB routines
csky: System Call
...
26 Oct, 2018
2 commits
-
The driver is for C-SKY APB bus interrupt controller. It's a simple
interrupt controller which use pending reg to detect the irq and use
enable/disable reg to mask/unmask interrupt sources.A lot of SOCs based on C-SKY CPU use the interrupt controller as root
controller.Signed-off-by: Guo Ren
Reviewed-by: Mark Rutland -
The driver is for C-SKY SMP interrupt controller. It support 16
soft-irqs, 16 private-irqs, and 992 max external-irqs, a total of
1024 interrupts.C-SKY CPU 807/810/860 SMP/non-SMP could use it.
Signed-off-by: Guo Ren
Reviewed-by: Marc Zyngier
02 Oct, 2018
1 commit
-
This is a cascaded interrupt controller in the AP806 GIC that collapses
SEIs (System Error Interrupt) coming from the AP and the CPs (through
the ICU).The SEI handles up to 64 interrupts. The first 21 interrupts are wired
from the AP. The next 43 interrupts are from the CPs and are triggered
through MSI messages. To handle this complexity, the driver has to
declare to the upper layer: one IRQ domain for the wired interrupts,
one IRQ domain for the MSIs; and acts as a MSI controller ('parent')
by declaring an MSI domain.Suggested-by: Haim Boot
Suggested-by: Marc Zyngier
Signed-off-by: Miquel Raynal
Signed-off-by: Marc Zyngier
13 Aug, 2018
1 commit
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Add a driver for the SiFive implementation of the RISC-V Platform Level
Interrupt Controller (PLIC). The PLIC connects global interrupt sources
to the local interrupt controller on each hart.This driver is based on the driver in the RISC-V tree from Palmer Dabbelt,
but has been almost entirely rewritten since, and includes many fixes
from Atish Patra.Signed-off-by: Christoph Hellwig
Acked-by: Thomas Gleixner
Reviewed-by: Atish Patra
[Binding update by Palmer]
Signed-off-by: Palmer Dabbelt
13 May, 2018
1 commit
-
GICv3 offers the possibility to signal SPIs using a pair of doorbells
(SETPI, CLRSPI) under the name of Message Based Interrupts (MBI).
They can be used as either traditional (edge) MSIs, or the more exotic
level-triggered flavour.Let's implement support for platform MSI, which is the original intent
for this feature.Signed-off-by: Marc Zyngier
Signed-off-by: Thomas Gleixner
Cc: Rob Herring
Cc: Jason Cooper
Cc: Ard Biesheuvel
Cc: Srinivas Kandagatla
Cc: Thomas Petazzoni
Cc: Miquel Raynal
Link: https://lkml.kernel.org/r/20180508121438.11301-8-marc.zyngier@arm.com
05 Apr, 2018
1 commit
-
Pull staging/IIO updates from Greg KH:
"Here is the big set of Staging/IIO driver patches for 4.17-rc1.It is a lot, over 500 changes, but not huge by previous kernel release
standards. We deleted more lines than we added again (27k added vs.
91k remvoed), thanks to finally being able to delete the IRDA drivers
and networking code.We also deleted the ccree crypto driver, but that's coming back in
through the crypto tree to you, in a much cleaned-up form.Added this round is at lot of "mt7621" device support, which is for an
embedded device that Neil Brown cares about, and of course a handful
of new IIO drivers as well.And finally, the fsl-mc core code moved out of the staging tree to the
"real" part of the kernel, which is nice to see happen as well.Full details are in the shortlog, which has all of the tiny cleanup
patches described.All of these have been in linux-next for a while with no reported
issues"* tag 'staging-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (579 commits)
staging: rtl8723bs: Remove yield call, replace with cond_resched()
staging: rtl8723bs: Replace yield() call with cond_resched()
staging: rtl8723bs: Remove unecessary newlines from 'odm.h'.
staging: rtl8723bs: Rework 'struct _ODM_Phy_Status_Info_' coding style.
staging: rtl8723bs: Rework 'struct _ODM_Per_Pkt_Info_' coding style.
staging: rtl8723bs: Replace NULL pointer comparison with '!'.
staging: rtl8723bs: Factor out rtl8723bs_recv_tasklet() sections.
staging: rtl8723bs: Fix function signature that goes over 80 characters.
staging: rtl8723bs: Fix lines too long in update_recvframe_attrib().
staging: rtl8723bs: Remove unnecessary blank lines in 'rtl8723bs_recv.c'.
staging: rtl8723bs: Change camel case to snake case in 'rtl8723bs_recv.c'.
staging: rtl8723bs: Add missing braces in else statement.
staging: rtl8723bs: Add spaces around ternary operators.
staging: rtl8723bs: Fix lines with trailing open parentheses.
staging: rtl8723bs: Remove unnecessary length #define's.
staging: rtl8723bs: Fix IEEE80211 authentication algorithm constants.
staging: rtl8723bs: Fix alignment in rtw_wx_set_auth().
staging: rtl8723bs: Remove braces from single statement conditionals.
staging: rtl8723bs: Remove unecessary braces from switch statement.
staging: rtl8723bs: Fix newlines in rtw_wx_set_auth().
...