21 Jan, 2020

1 commit

  • The Aspeed SOCs provide some interrupts through the System Control
    Unit registers. Add an interrupt controller that provides these
    interrupts to the system.

    Signed-off-by: Eddie James
    Signed-off-by: Marc Zyngier
    Reviewed-by: Andrew Jeffery
    Link: https://lore.kernel.org/r/1579123790-6894-3-git-send-email-eajames@linux.ibm.com

    Eddie James