06 Aug, 2020
2 commits
-
- Fix several kerneldoc warnings (Krzysztof Kozlowski)
* pci/doc:
PCI: Fix kerneldoc warnings -
Fix kerneldoc warnings, e.g.,
$ make W=1 drivers/pci/
drivers/pci/ats.c:196: warning: Function parameter or member 'pdev' not described in 'pci_enable_pri'
drivers/pci/ats.c:196: warning: Function parameter or member 'reqs' not described in 'pci_enable_pri'
...Link: https://lore.kernel.org/r/20200729201224.26799-2-krzk@kernel.org
Link: https://lore.kernel.org/r/20200729201224.26799-3-krzk@kernel.org
Link: https://lore.kernel.org/r/20200729201224.26799-4-krzk@kernel.org
Link: https://lore.kernel.org/r/20200729201224.26799-5-krzk@kernel.org
Link: https://lore.kernel.org/r/20200729201224.26799-6-krzk@kernel.org
Link: https://lore.kernel.org/r/20200729201224.26799-7-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski
Signed-off-by: Bjorn Helgaas
24 Jul, 2020
1 commit
-
For SR-IOV, the PF PRI is shared between the PF and any associated VFs, and
the PRI Capability is allowed for PFs but not for VFs. Searching for the
PRI Capability on a VF always fails, even if its associated PF supports
PRI.Add pci_pri_supported() to check whether device or its associated PF
supports PRI.[bhelgaas: commit log, avoid "!!"]
Fixes: b16d0cb9e2fc ("iommu/vt-d: Always enable PASID/PRI PCI capabilities before ATS")
Link: https://lore.kernel.org/r/1595543849-19692-1-git-send-email-ashok.raj@intel.com
Signed-off-by: Ashok Raj
Signed-off-by: Bjorn Helgaas
Reviewed-by: Lu Baolu
Acked-by: Joerg Roedel
Cc: stable@vger.kernel.org # v4.4+
27 May, 2020
1 commit
-
Add pci_ats_supported(), which checks whether a device has an ATS
capability, and whether it is trusted. A device is untrusted if it is
plugged into an external-facing port such as Thunderbolt and could be
spoofing an existing device to exploit weaknesses in the IOMMU
configuration. PCIe ATS is one such weaknesses since it allows
endpoints to cache IOMMU translations and emit transactions with
'Translated' Address Type (10b) that partially bypass the IOMMU
translation.The SMMUv3 and VT-d IOMMU drivers already disallow ATS and transactions
with 'Translated' Address Type for untrusted devices. Add the check to
pci_enable_ats() to let other drivers (AMD IOMMU for now) benefit from
it.By checking ats_cap, the pci_ats_supported() helper also returns whether
ATS was globally disabled with pci=noats, and could later include more
things, for example whether the whole PCIe hierarchy down to the
endpoint supports ATS.Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Joerg Roedel
Acked-by: Bjorn Helgaas
Link: https://lore.kernel.org/r/20200520152201.3309416-2-jean-philippe@linaro.org
Signed-off-by: Joerg Roedel
19 Mar, 2020
1 commit
-
The Arm SMMUv3 driver uses pci_{enable,disable}_pasid() and related
functions. Export them to allow the driver to be built as a module.Acked-by: Bjorn Helgaas
Signed-off-by: Jean-Philippe Brucker
Signed-off-by: Will Deacon
06 Feb, 2020
2 commits
-
Pull PCI fixes from Bjorn Helgaas:
- Define to_pci_sysdata() always to fix build breakage when !CONFIG_PCI
(Jason A. Donenfeld)- Use PF PASID for VFs to fix VF IOMMU bind failures (Kuppuswamy
Sathyanarayanan)* tag 'pci-v5.6-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI/ATS: Use PF PASID for VFs
x86/PCI: Define to_pci_sysdata() even when !CONFIG_PCI -
Per PCIe r5.0, sec 9.3.7.14, if a PF implements the PASID Capability, the
PF PASID configuration is shared by its VFs, and VFs must not implement
their own PASID Capability. But commit 751035b8dc06 ("PCI/ATS: Cache PASID
Capability offset") changed pci_max_pasids() and pci_pasid_features() to
use the PASID Capability of the VF device instead of the associated PF
device. This leads to IOMMU bind failures when pci_max_pasids() and
pci_pasid_features() are called for VFs.In pci_max_pasids() and pci_pasid_features(), always use the PF PASID
Capability.Fixes: 751035b8dc06 ("PCI/ATS: Cache PASID Capability offset")
Link: https://lore.kernel.org/r/fe891f9755cb18349389609e7fed9940fc5b081a.1580325170.git.sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas
CC: stable@vger.kernel.org # v5.5+
23 Dec, 2019
1 commit
-
Commit d355bb209783 ("PCI/ATS: Remove unnecessary EXPORT_SYMBOL_GPL()")
unexported a bunch of symbols from the PCI core since the only external
users were non-modular IOMMU drivers. Although most of those symbols
can remain private for now, 'pci_{enable,disable_ats()' is required for
the ARM SMMUv3 driver to build as a module, otherwise we get a build
failure as follows:| ERROR: "pci_enable_ats" [drivers/iommu/arm-smmu-v3.ko] undefined!
| ERROR: "pci_disable_ats" [drivers/iommu/arm-smmu-v3.ko] undefined!Re-export these two functions so that the ARM SMMUv3 driver can be build
as a module.Cc: Bjorn Helgaas
Cc: Joerg Roedel
Signed-off-by: Greg Kroah-Hartman
[will: rewrote commit message]
Signed-off-by: Will Deacon
Tested-by: John Garry # smmu v3
Reviewed-by: Greg Kroah-Hartman
Acked-by: Bjorn Helgaas
Signed-off-by: Joerg Roedel
16 Oct, 2019
8 commits
-
The following functions are only used by the PCI core or by IOMMU drivers
that cannot be modular, so there's no need to export them at all:pci_enable_ats()
pci_disable_ats()
pci_restore_ats_state()
pci_ats_queue_depth()
pci_ats_page_aligned()pci_enable_pri()
pci_restore_pri_state()
pci_reset_pri()
pci_prg_resp_pasid_required()pci_enable_pasid()
pci_disable_pasid()
pci_restore_pasid_state()
pci_pasid_features()
pci_max_pasids()Remove the unnecessary EXPORT_SYMBOL_GPL()s.
Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel -
The PRG Response PASID Required bit in the PRI Capability is read-only.
Read it once when we enumerate the device and cache the value so we don't
need to read it again.Based-on-patch-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas -
Previously each PASID interface searched for the PASID Capability. Cache
the capability offset the first time we use it instead of searching each
time.[bhelgaas: commit log, reorder patch to later, call pci_pasid_init() from
pci_init_capabilities()]
Link: https://lore.kernel.org/r/4957778959fa34eab3e8b3065d1951989c61cb0f.1567029860.git.sathyanarayanan.kuppuswamy@linux.intel.com
Link: https://lore.kernel.org/r/20190905193146.90250-6-helgaas@kernel.org
Signed-off-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas -
Previously each PRI interface searched for the PRI Capability. Cache the
capability offset the first time we use it instead of searching each time.[bhelgaas: commit log, reorder patch to later, call pci_pri_init() from
pci_init_capabilities()]
Link: https://lore.kernel.org/r/0c5495d376faf6dbb8eb2165204c474438aaae65.156
7029860.git.sathyanarayanan.kuppuswamy@linux.intel.com
Link: https://lore.kernel.org/r/20190905193146.90250-5-helgaas@kernel.org
Signed-off-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas -
Previously we didn't disable the PF ATS until all associated VFs had
disabled it. But per PCIe spec r5.0, sec 9.3.7.8, the ATS Capability in
VFs and associated PFs may be enabled independently. Leaving ATS enabled
in the PF unnecessarily may have power and performance impacts.Remove this dependency logic in the ATS enable/disable code.
[bhelgaas: commit log]
Suggested-by: Ashok Raj
Link: https://lore.kernel.org/r/8163ab8fa66afd2cba514ae95d29ab12104781aa.1567029860.git.sathyanarayanan.kuppuswamy@linux.intel.com
Link: https://lore.kernel.org/r/20190905193146.90250-4-helgaas@kernel.org
Signed-off-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas
Cc: Ashok Raj
Cc: Keith Busch -
Per PCIe r5.0, sec 9.3.7.14, if a PF implements the PASID Capability, the
PF PASID configuration is shared by its VFs. VFs must not implement their
own PASID Capability. Since VFs don't have a PASID Capability,
pci_enable_pasid() always failed, which caused IOMMU setup to fail.Update the PASID interfaces so for VFs they reflect the state of the PF
PASID.[bhelgaas: rebase without pasid_cap caching, commit log]
Suggested-by: Ashok Raj
Link: https://lore.kernel.org/r/8ba1ac192e4ac737508b6ac15002158e176bab91.1567029860.git.sathyanarayanan.kuppuswamy@linux.intel.com
Link: https://lore.kernel.org/r/20190905193146.90250-3-helgaas@kernel.org
Signed-off-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas
Cc: Ashok Raj
Cc: Keith Busch -
Per PCIe r5.0, sec 9.3.7.11, VFs must not implement the PRI Capability. If
the PF implements PRI, it is shared by the VFs. Since VFs don't have a PRI
Capability, pci_enable_pri() always failed, which caused IOMMU setup to
fail.Update the PRI interfaces so for VFs they reflect the state of the PF PRI.
[bhelgaas: rebase without pri_cap caching, commit log]
Suggested-by: Ashok Raj
Link: https://lore.kernel.org/r/b971e31f8695980da8e4a7f93e3b6a3edba3edaa.1567029860.git.sathyanarayanan.kuppuswamy@linux.intel.com
Link: https://lore.kernel.org/r/20190905193146.90250-2-helgaas@kernel.org
Signed-off-by: Kuppuswamy Sathyanarayanan
Signed-off-by: Bjorn Helgaas
Cc: Ashok Raj
Cc: Keith Busch -
pci_prg_resp_pasid_required() returns the value of the "PRG Response PASID
Required" bit from the PRI capability, but the interface was previously
defined under #ifdef CONFIG_PCI_PASID.Move it from CONFIG_PCI_PASID to CONFIG_PCI_PRI so it's with the other
PRI-related things.Signed-off-by: Bjorn Helgaas
Reviewed-by: Kuppuswamy Sathyanarayanan
Reviewed-by: Joerg Roedel
09 Jul, 2019
1 commit
-
Fix typos in drivers/pci. Comment and whitespace changes only.
Signed-off-by: Bjorn Helgaas
Reviewed-by: Rafael J. Wysocki
Reviewed-by: Randy Dunlap
26 Feb, 2019
2 commits
-
Return the Page Aligned Request bit in the ATS Capability Register.
As per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit is
set, it indicates the Untranslated Addresses generated by the device are
always aligned to a 4096 byte boundary.An IOMMU that can only translate page-aligned addresses can only be used
with devices that always produce aligned Untranslated Addresses. This
interface will be used by drivers for such IOMMUs to determine whether
devices can use the ATS service.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Keith Busch
Suggested-by: Ashok Raj
Signed-off-by: Kuppuswamy Sathyanarayanan
Acked-by: Bjorn Helgaas
Signed-off-by: Joerg Roedel -
Return the PRG Response PASID Required bit in the Page Request
Status Register.As per PCIe spec r4.0, sec 10.5.2.3, if this bit is Set, the device
expects a PASID TLP Prefix on PRG Response Messages when the
corresponding Page Requests had a PASID TLP Prefix. If Clear, the device
does not expect PASID TLP Prefixes on any PRG Response Message, and the
device behavior is undefined if the device receives a PRG Response Message
with a PASID TLP Prefix. Also the device behavior is undefined if this
bit is Set and the device receives a PRG Response Message with no PASID TLP
Prefix when the corresponding Page Requests had a PASID TLP Prefix.This function will be used by drivers like IOMMU, if it is required to
check the status of the PRG Response PASID Required bit before enabling
the PASID support of the device.Cc: Ashok Raj
Cc: Jacob Pan
Cc: Keith Busch
Suggested-by: Ashok Raj
Signed-off-by: Kuppuswamy Sathyanarayanan
Acked-by: Bjorn Helgaas
Signed-off-by: Joerg Roedel
01 Jul, 2018
1 commit
-
A PCIe endpoint carries the process address space identifier (PASID) in
the TLP prefix as part of the memory read/write transaction. The address
information in the TLP is relevant only for a given PASID context.An IOMMU takes PASID value and the address information from the
TLP to look up the physical address in the system.PASID is an End-End TLP Prefix (PCIe r4.0, sec 6.20). Sec 2.2.10.2 says
It is an error to receive a TLP with an End-End TLP Prefix by a
Receiver that does not support End-End TLP Prefixes. A TLP in
violation of this rule is handled as a Malformed TLP. This is a
reported error associated with the Receiving Port (see Section 6.2).Prevent error condition by proactively requiring End-End TLP prefix to be
supported on the entire data path between the endpoint and the root port
before enabling PASID.Signed-off-by: Sinan Kaya
Signed-off-by: Bjorn Helgaas
11 May, 2018
1 commit
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Adds a "pci=noats" boot parameter. When supplied, all ATS related
functions fail immediately and the IOMMU is configured to not use
device-IOTLB.Any function that checks for ATS capabilities directly against the devices
should also check this flag. Currently, such functions exist only in IOMMU
drivers, and they are covered by this patch.The motivation behind this patch is the existence of malicious devices.
Lots of research has been done about how to use the IOMMU as protection
from such devices. When ATS is supported, any I/O device can access any
physical address by faking device-IOTLB entries. Adding the ability to
ignore these entries lets sysadmins enhance system security.Signed-off-by: Gil Kupfer
Signed-off-by: Bjorn Helgaas
Acked-by: Joerg Roedel
20 Mar, 2018
1 commit
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Remove pointless comments that tell us the file name, remove blank line
comments, follow multi-line comment conventions. No functional change
intended.Signed-off-by: Bjorn Helgaas
27 Jan, 2018
1 commit
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b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license") added SPDX GPL-2.0 to several PCI files that
previously contained no license information.Add SPDX GPL-2.0 to all other PCI files that did not contain any license
information and hence were under the default GPL version 2 license of the
kernel.Signed-off-by: Bjorn Helgaas
Reviewed-by: Greg Kroah-Hartman
31 May, 2017
2 commits
-
After a Function-Level Reset, PCI states need to be restored. Save PASID
features and PRI reqs cached.[bhelgaas: search for capability only if PRI/PASID were enabled]
Signed-off-by: CQ Tang
Signed-off-by: Ashok Raj
Signed-off-by: Bjorn Helgaas
Cc: Joerg Roedel
Cc: Jean-Phillipe Brucker
Cc: David Woodhouse -
Device drivers need to check if an IOMMU enabled ATS, PRI and PASID in
order to know when they can use the SVM API. Cache PRI and PASID bits in
the pci_dev structure, similarly to what is currently done for ATS.Signed-off-by: Jean-Philippe Brucker
Signed-off-by: Bjorn Helgaas
14 Aug, 2015
8 commits
-
Remove pci_ats_enabled(). There are no callers outside the ATS code
itself. We don't need to check ats_cap, because if we don't find an ATS
capability, we'll never set ats_enabled.Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel -
Stop caching the Invalidate Queue Depth in struct pci_dev.
pci_ats_queue_depth() is typically called only once per device, and it
returns a fixed value per-device, so callers who need the value frequently
can cache it themselves.Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel -
There's no need to BUG() if we enable ATS when it's already enabled. We
don't need to BUG() when disabling ATS on a device that doesn't support ATS
or if it's already disabled. If ATS is enabled, certainly we found an ATS
capability in the past, so it should still be there now.Clean up these error paths.
Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel -
Use the pci_physfn() helper rather than looking up physfn by hand.
No functional change.Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel -
The ATS setup code in ats_alloc_one() is only used by pci_ats_init(), so
inline it there. No functional change.Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel -
We previously returned -ENODEV for devices that don't support ATS (except
that we always returned 0 for VFs, whether or not they support ATS).For consistency, always return -EINVAL (not -ENODEV) if the device doesn't
support ATS. Return zero for VFs that support ATS.Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel -
The pci_ats struct is small and will get smaller, so I don't think it's
worth allocating it separately from the pci_dev struct.Embed the ATS fields directly into struct pci_dev.
Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel -
Previously, we allocated pci_ats structures when an IOMMU driver called
pci_enable_ats(). An SR-IOV VF shares the STU setting with its PF, so when
enabling ATS on the VF, we allocated a pci_ats struct for the PF if it
didn't already have one. We held the sriov->lock to serialize threads
concurrently enabling ATS on several VFS so only one would allocate the PF
pci_ats.Gregor reported a deadlock here:
pci_enable_sriov
sriov_enable
virtfn_add
mutex_lock(dev->sriov->lock) # acquire sriov->lock
pci_device_add
device_add
BUS_NOTIFY_ADD_DEVICE notifier chain
iommu_bus_notifier
amd_iommu_add_device # iommu_ops.add_device
init_iommu_group
iommu_group_get_for_dev
iommu_group_add_device
__iommu_attach_device
amd_iommu_attach_device # iommu_ops.attach_device
attach_device
pci_enable_ats
mutex_lock(dev->sriov->lock) # deadlockThere's no reason to delay allocating the pci_ats struct, and if we
allocate it for each device at enumeration-time, there's no need for
locking in pci_enable_ats().Allocate pci_ats struct during enumeration, when we initialize other
capabilities.Note that this implementation requires ATS to be enabled on the PF first,
before on any of the VFs because the PF controls the STU for all the VFs.Link: http://permalink.gmane.org/gmane.linux.kernel.iommu/9433
Reported-by: Gregor Dick
Signed-off-by: Bjorn Helgaas
Reviewed-by: Joerg Roedel
11 Jan, 2014
1 commit
-
My philosophy is unused code is dead code. And dead code is subject to bit
rot and is a likely source of bugs. Use it or lose it.This reverts parts of c320b976d783 ("PCI: Add implementation for PRI
capability"), removing these interfaces:pci_pri_enabled()
pci_pri_stopped()
pci_pri_status()[bhelgaas: split to separate patch]
Signed-off-by: Stephen Hemminger
Signed-off-by: Bjorn Helgaas
CC: Joerg Roedel
15 Nov, 2013
1 commit
-
Fix whitespace, capitalization, and spelling errors. No functional change.
I know "busses" is not an error, but "buses" was more common, so I used it
consistently.Signed-off-by: Marta Rybczynska (pci_reset_bridge_secondary_bus())
Signed-off-by: Bjorn Helgaas
Acked-by: Rafael J. Wysocki
12 Jan, 2012
1 commit
-
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci: (80 commits)
x86/PCI: Expand the x86_msi_ops to have a restore MSIs.
PCI: Increase resource array mask bit size in pcim_iomap_regions()
PCI: DEVICE_COUNT_RESOURCE should be equal to PCI_NUM_RESOURCES
PCI: pci_ids: add device ids for STA2X11 device (aka ConneXT)
PNP: work around Dell 1536/1546 BIOS MMCONFIG bug that breaks USB
x86/PCI: amd: factor out MMCONFIG discovery
PCI: Enable ATS at the device state restore
PCI: msi: fix imbalanced refcount of msi irq sysfs objects
PCI: kconfig: English typo in pci/pcie/Kconfig
PCI/PM/Runtime: make PCI traces quieter
PCI: remove pci_create_bus()
xtensa/PCI: convert to pci_scan_root_bus() for correct root bus resources
x86/PCI: convert to pci_create_root_bus() and pci_scan_root_bus()
x86/PCI: use pci_scan_bus() instead of pci_scan_bus_parented()
x86/PCI: read Broadcom CNB20LE host bridge info before PCI scan
sparc32, leon/PCI: convert to pci_scan_root_bus() for correct root bus resources
sparc/PCI: convert to pci_create_root_bus()
sh/PCI: convert to pci_scan_root_bus() for correct root bus resources
powerpc/PCI: convert to pci_create_root_bus()
powerpc/PCI: split PHB part out of pcibios_map_io_space()
...Fix up conflicts in drivers/pci/msi.c and include/linux/pci_regs.h due
to the same patches being applied in other branches.
09 Jan, 2012
1 commit
-
Conflicts:
drivers/pci/hotplug/acpiphp_glue.c
07 Jan, 2012
2 commits
-
During S3 or S4 resume or PCI reset, ATS regs aren't restored correctly.
This patch enables ATS at the device state restore if PCI device has ATS
capability.Signed-off-by: Xudong Hao
Signed-off-by: Xiantao Zhang
Signed-off-by: Jesse Barnes -
These are extended capabilities, rename and move to proper
group for consistency.Signed-off-by: Alex Williamson
Signed-off-by: Jesse Barnes
06 Dec, 2011
1 commit
-
I get this compile failure on parisc:
drivers/pci/ats.c: In function 'ats_alloc_one':
drivers/pci/ats.c:29: error: implicit declaration of function 'kzalloc'
drivers/pci/ats.c:29: warning: assignment makes pointer from integer without a cast
drivers/pci/ats.c: In function 'ats_free_one':
drivers/pci/ats.c:45: error: implicit declaration of function 'kfree'Because ats.c is missing linux/slab.h as an include. This patch fixes it
Signed-off-by: James Bottomley
Signed-off-by: Jesse Barnes
