09 Dec, 2020
1 commit
-
Mistakenly the buffers (input and output) become enabled together for a short
period of time during GPIO request. This is problematic, because instead of
initial motive to disable them in the commit af7e3eeb84e2
("pinctrl: intel: Disable input and output buffer when switching to GPIO"),
the driven value on the pin, which might be used as an IRQ line, brings
firmwares of some touch pads to an awkward state that needs a full power off
to recover. Fix this, as stated in the culprit commit, by disabling the buffers.Fixes: af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO")
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=210497
Reported-by: Pierre-Louis Bossart
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
Tested-by: Pierre-Louis Bossart
Tested-by: Kai-Heng Feng
Link: https://lore.kernel.org/r/20201208182403.40435-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij
16 Nov, 2020
4 commits
-
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.Fixes: 658b476c742f ("pinctrl: baytrail: Add debounce configuration")
Depends-on: 04ff5a095d66 ("pinctrl: baytrail: Rectify debounce support")
Depends-on: 827e1579e1d5 ("pinctrl: baytrail: Rectify debounce support (part 2)")
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible
because it gives a good trade off between weakness and minimization of leakage
current (will be only 50 uA with the above choice).Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips")
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.Fixes: e278dcb7048b1 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Cc: stable@vger.kernel.org
Signed-off-by: Evan Green
Acked-by: Mika Westerberg
Signed-off-by: Andy Shevchenko -
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
26 Oct, 2020
2 commits
-
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.In case of Intel pin control hardware the 5 kOhm sounds plausible
because on one hand it's a minimum of resistors present in all
hardware generations and at the same time it's high enough to minimize
leakage current (will be only 200 uA with the above choice).Fixes: e57725eabf87 ("pinctrl: intel: Add support for hardware debouncer")
Reported-by: Jamie McClymont
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
2 kOhm bias was never an option in Intel GPIO hardware, the available
matrix is:000 none
001 1 kOhm (if available)
010 5 kOhm
100 20 kOhmAs easy to get the 3 resistors are gated separately and according to
parallel circuits calculations we may get combinations of the above where
the result is always strictly less than minimal resistance. Hence,
additional values can be:011 ~833.3 Ohm
101 ~952.4 Ohm
110 ~4 kOhm
111 ~800 OhmThat said, convert TERM definitions to be the bit masks to reflect the above.
While at it, enable the same setting for pull down case.
Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
Cc: Jamie McClymont
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
30 Sep, 2020
3 commits
-
Modify COMMUNITY macros to be consistent with Tiger Lake and others.
No functional change intended.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
Link: https://lore.kernel.org/r/20200929110306.40852-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij -
Modify COMMUNITY macros to be consistent with Tiger Lake and others.
No functional change intended.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
Link: https://lore.kernel.org/r/20200929110306.40852-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij -
It appears that almost traditionally the H variants have some deviations
in the register offsets in comparison to LP ones. This is the case for
Intel Tiger Lake as well. Fix register offsets for TGL-H variant.Fixes: 653d96455e1e ("pinctrl: tigerlake: Add support for Tiger Lake-H")
Reported-by: Pierre-Louis Bossart
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
Link: https://lore.kernel.org/r/20200929110306.40852-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij
07 Sep, 2020
1 commit
-
One some devices the GPIO should output the inverted value from what
device-drivers / ACPI code expects. The reason for this is unknown,
perhaps these systems use an external buffer chip on the GPIO which
inverts the signal. The BIOS makes this work by setting the
CHV_PADCTRL1_INVRXTX_TXDATA flag.Before this commit we would unconditionally clear all INVRXTX flags,
including the CHV_PADCTRL1_INVRXTX_TXDATA flag when a GPIO is requested
by a driver (from chv_gpio_request_enable()).This breaks systems using this setup. Specifically it is causing
problems for systems with a goodix touchscreen, where the BIOS sets the
INVRXTX_TXDATA flag on the GPIO used for the touchscreen's reset pin.The goodix touchscreen driver by defaults configures this pin as input
(relying on the pull-up to keep it high), but the clearing of the
INVRXTX_TXDATA flag done by chv_gpio_request_enable() causes it to be
driven low for a brief time before the GPIO gets set to input mode.This causes the touchscreen controller to get reset. On most CHT devs
with this touchscreen this leads to:[ 31.596534] Goodix-TS i2c-GDIX1001:00: i2c test failed attempt 1: -121
The driver retries this though and then everything is fine. But during
reset the touchscreen uses its interrupt pin as bootstrap to determine
which i2c address to use and on the Acer One S1003 the spurious reset
caused by the clearing of the INVRXTX_TXDATA flag causes the controller
to come back up again on the wrong i2c address, breaking things.This commit fixes both the -121 errors, as well as the total breakage
on the Acer One S1003, by making chv_gpio_clear_triggering() not clear
the INVRXTX_TXDATA flag if the pin is already configured as a GPIO.Note that chv_pinmux_set_mux() does still unconditionally clear the
flag, so this only affects GPIO usage.Fixes: a7d4b171660c ("Input: goodix - add support for getting IRQ + reset GPIOs on Cherry Trail devices")
Signed-off-by: Hans de Goede
Acked-by: Mika Westerberg
Signed-off-by: Andy Shevchenko
20 Aug, 2020
3 commits
-
Update header inclusion block to reflect all direct dependencies
that are being involved in pinctrl-intel.h.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Since we have common helper to retrieve SoC data from driver data
we may switch to use it.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Since we have common helper to retrieve SoC data from driver data
we may switch to use it.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
18 Aug, 2020
5 commits
-
intel_pinctrl_get_soc_data() helper can be used in few driver instead of
open-coded variants. Thus, extract it as a standalone API.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
By one of the previous clean up change we got a temporary variable to hold
a device pointer. It can be utilized in other calls in the ->probe() and
save a bit of LOCs.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Now when all preparations are done we may easily switch to use
struct intel_pinctrl instead of custom one.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
This is a preparatory patch for bigger clean up pending for Cherryview driver.
There is no functional change intended.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
There is no more .groups member in struct chv_pinctrl,
drop associated comment because it's not applicable anymore.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
21 Jul, 2020
1 commit
-
This driver adds pinctrl/GPIO support for Intel Emmitsburg PCH. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.Signed-off-by: Andy Shevchenko
Reviewed-by: Linus Walleij
Acked-by: Mika Westerberg
19 Jul, 2020
1 commit
-
Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1].[1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through
Signed-off-by: Gustavo A. R. Silva
Signed-off-by: Andy Shevchenko
29 Jun, 2020
2 commits
-
Intel Tiger Lake-H has different pin layout than the -LP variant
so add support for this to the existing Tiger Lake driver.Signed-off-by: Mika Westerberg
Signed-off-by: Andy Shevchenko -
It is useful to control I²S bus 2 pins if we would like to connect
an audio codec.Reported-by: mouse
Reported-by: Pierre-Louis Bossart
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg
23 Jun, 2020
1 commit
-
Some of the pin names were provided officially to the customers
in different spelling. We update pin names in accordance with
the official list.Signed-off-by: Andy Shevchenko
22 Jun, 2020
16 commits
-
The pins on the Bay Trail SoC have separate input-buffer and output-buffer
enable bits and a read of the level bit of the value register will always
return the value from the input-buffer.The BIOS of a device may configure a pin in output-only mode, only enabling
the output buffer, and write 1 to the level bit to drive the pin high.
This 1 written to the level bit will be stored inside the data-latch of the
output buffer.But a subsequent read of the value register will return 0 for the level bit
because the input-buffer is disabled. This causes a read-modify-write as
done by byt_gpio_set_direction() to write 0 to the level bit, driving the
pin low!Before this commit byt_gpio_direction_output() relied on
pinctrl_gpio_direction_output() to set the direction, followed by a call
to byt_gpio_set() to apply the selected value. This causes the pin to
go low between the pinctrl_gpio_direction_output() and byt_gpio_set()
calls.Change byt_gpio_direction_output() to directly make the register
modifications itself instead. Replacing the 2 subsequent writes to the
value register with a single write.Note that the pinctrl code does not keep track internally of the direction,
so not going through pinctrl_gpio_direction_output() is not an issue.This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is
already on at boot (no external monitor connected), then the i915 driver
does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The
temporarily going low of that GPIO was causing the panel to reset itself
after which it would not show an image until it was turned off and back on
again (until a full modeset was done on it). This commit fixes this.This commit also updates the byt_gpio_direction_input() to use direct
register accesses instead of going through pinctrl_gpio_direction_input(),
to keep it consistent with byt_gpio_direction_output().Note for backporting, this commit depends on:
commit e2b74419e5cc ("pinctrl: baytrail: Replace WARN with dev_info_once
when setting direct-irq pin to output")Cc: stable@vger.kernel.org
Fixes: 86e3ef812fe3 ("pinctrl: baytrail: Update gpio chip operations")
Signed-off-by: Hans de Goede
Acked-by: Mika Westerberg
Signed-off-by: Andy Shevchenko -
Since we dependent on ACPI, there is no need to use ACPI_PTR()
which is a no-op in this case.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Since we dependent on ACPI, there is no need to use ACPI_PTR()
which is a no-op in this case.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Introduce couple of helpers to enable or disable input. i.e.
lp_gpio_enable_input() and lp_gpio_disable_input().Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Make use of for_each_requested_gpio() instead of home grown analogue.
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Make use of for_each_requested_gpio_in_range() instead of home grown analogue.
Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Protect IO in intel_gpio_get_direction(), intel_gpio_community_irq_handler(),
intel_config_get_debounce() and intel_config_get_pull() by lock. Even for
simple readl() we better serialize IO to avoid potential problems.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Split intel_config_get() to three functions, i.e. intel_config_get() and
two helpers intel_config_get_pull() and intel_config_get_debounce() to be
symmetrical with intel_config_set*().Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Drop the only label in the code, i.e. in intel_config_set_debounce(),
for consistency with the rest. In entire driver we use multipoint
return.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
In a code like
if (...) {
...
goto label;
} else {
...
}
the 'else' keyword is redundant. Get rid of it for better readability.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
Instead of using bitwise operations against returned values,
which is a bit fragile, convert IRQ handler to count amount of
GPIO groups, where at least one interrupt happened, and convert
it to returned value by IRQ_RETVAL() macro.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
In some cases lock covers unneeded calls and operations.
Reduce scope of the lock in such cases.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
It's possible scenario that pin has been in different mode, while
the respective GPIO register has a leftover output buffer enabled.
In such case when we request GPIO it will switch to GPIO mode, and
thus to output with unknown value, followed by switching to input
mode. This can produce a glitch on the pin.Disable input and output buffer when switching to GPIO to avoid
potential glitches.Signed-off-by: Andy Shevchenko
Acked-by: Mika Westerberg -
We have some data structures duplicated across the drivers.
Let's deduplicate them by using struct intel_pinctrl_soc_data,
struct intel_community and struct intel_pinctrl_context that
are being provided by pinctrl-intel.h.Signed-off-by: Andy Shevchenko
Acked-by: Linus Walleij
Acked-by: Mika Westerberg -
Individual drivers may install ACPI OpRegion handlers based on
address space ID which differs from community to community.
Add special field in the struct intel_community for that purpose.Signed-off-by: Andy Shevchenko
Acked-by: Linus Walleij
Acked-by: Mika Westerberg -
Some of the pin control devices may not be capable to generate IRQ
per each pin in the community. Allow individual drivers to define
total amount of IRQs per community.Signed-off-by: Andy Shevchenko
Acked-by: Linus Walleij
Acked-by: Mika Westerberg