Eric Lee / smarc-fsl-linux-kernel

09 Oct, 2020

1 commit

  • d6bbd1193   spi: dw: Add DWC SSI capability ... Browse Code »

    Currently DWC SSI core is supported by means of setting up the
    core-specific update_cr0() callback. It isn't suitable for multiple
    reasons. First of all having exported several methods doing the same thing
    but for different chips makes the code harder to maintain. Secondly the
    spi-dw-core driver exports the methods, then the spi-dw-mmio driver sets
    the private data callback with one of them so to be called by the core
    driver again. That makes the code logic too complicated. Thirdly using
    callbacks for just updating the CR0 register is problematic, since in case
    if the register needed to be updated from different parts of the code,
    we'd have to create another callback (for instance the SPI device-specific
    parameters don't need to be calculated each time the SPI transfer is
    submitted, so it's better to pre-calculate the CR0 data at the SPI-device
    setup stage).

    So keeping all the above in mind let's discard the update_cr0() callbacks,
    define a generic and static dw_spi_update_cr0() method and create the
    DW_SPI_CAP_DWC_SSI capability, which when enabled would activate the
    alternative CR0 register layout.

    While at it add the comments to the code path of the normal DW APB SSI
    controller setup to make the dw_spi_update_cr0() method looking coherent.

    Signed-off-by: Serge Semin
    Link: https://lore.kernel.org/r/20201007235511.4935-3-Sergey.Semin@baikalelectronics.ru
    Signed-off-by: Mark Brown

    Serge Semin
     

30 Sep, 2020

2 commits

  • ffb7ca54c   spi: dw: Add KeemBay Master capability ... Browse Code »

    In a further commit we'll have to get rid of the update_cr0() callback and
    define a DW SSI capability instead. Since Keem Bay master/slave
    functionality is controller by the CTRL0 register bitfield, we need to
    first move the master mode selection into the internal corresponding
    update_cr0 method, which would be activated by means of the dedicated
    DW_SPI_CAP_KEEMBAY_MST capability setup.

    Note this will be also useful if the driver will be ever altered to
    support the DW SPI slave interface.

    Signed-off-by: Serge Semin
    Link: https://lore.kernel.org/r/20200920112914.26501-11-Sergey.Semin@baikalelectronics.ru
    Signed-off-by: Mark Brown

    Serge Semin
     
  • cc760f314   spi: dw: Convert CS-override to DW SPI capabilities ... Browse Code »

    There are several vendor-specific versions of the DW SPI controllers,
    each of which may have some peculiarities with respect to the original
    IP-core. Seeing it has already caused adding flags and a callback into the
    DW SPI private data, let's introduce a generic capabilities interface to
    tune the generic DW SPI controller driver up in accordance with the
    particular controller specifics. It's done by converting a simple
    Alpine-specific CS-override capability into the DW SPI controller
    capability activated by setting the DW_SPI_CAP_CS_OVERRIDE flag.

    Signed-off-by: Serge Semin
    Link: https://lore.kernel.org/r/20200920112914.26501-10-Sergey.Semin@baikalelectronics.ru
    Signed-off-by: Mark Brown

    Serge Semin
     

08 Sep, 2020

1 commit

  • 53a09635c   spi: dw: Add Microchip Sparx5 support ... Browse Code »

    This adds SPI support for the Sparx5 SoC, which is using the MMIO
    Designware SPI controller.

    The Sparx5 differs from the Ocelot version in these areas:

    * The CS override is controlled by a new set of registers for
    this purpose.

    * The Sparx5 SPI controller has the RX sample delay register, and it
    must be configured for the (SPI NAND) device on SPI2.

    * The Sparx5 SPI controller has 2 different SPI bus interfaces on the
    same controller (don't ask...). The "spi-mux" driver should be used
    in conjunction with the SPI driver to select the appropriate bus.

    Signed-off-by: Lars Povlsen
    Link: https://lore.kernel.org/r/20200824203010.2033-3-lars.povlsen@microchip.com
    Signed-off-by: Mark Brown

    Lars Povlsen
     

30 May, 2020

2 commits

  • 08ba93064   Merge series "spi: dw: Add generic DW DMA controller support" from Serge Semin <… ... Browse Code »

    …Sergey.Semin@baikalelectronics.ru>:

    Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals
    Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
    APB SSI devices embedded into the SoC. Currently the DMA-based transfers
    are supported by the DW APB SPI driver only as a middle layer code for
    Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal
    platform DMAC device we introduced a set of patches to fix it within this
    series.

    First of all we need to add the Tx and Rx DMA channels support into the DW
    APB SSI binding. Then there are several fixes and cleanups provided as a
    initial preparation for the Generic DMA support integration: add Tx/Rx
    finish wait methods, clear DMAC register when done or stopped, Fix native
    CS being unset, enable interrupts in accordance with DMA xfer mode,
    discard static DW DMA slave structures, discard unused void priv pointer
    and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst
    length parametrisation and make sure it's optionally set in accordance
    with the DMA max-burst capability.

    In order to have the DW APB SSI MMIO driver working with DMA we need to
    initialize the paddr field with the physical base address of the DW APB SSI
    registers space. Then we unpin the Intel MID specific code from the
    generic DMA one and placed it into the spi-dw-pci.c driver, which is a
    better place for it anyway. After that the naming cleanups are performed
    since the code is going to be used for a generic DMAC device. Finally the
    Generic DMA initialization can be added to the generic version of the
    DW APB SSI IP.

    Last but not least we traditionally convert the legacy plain text-based
    dt-binding file with yaml-based one and as a cherry on a cake replace
    the manually written DebugFS registers read method with a ready-to-use
    for the same purpose regset32 DebugFS interface usage.

    This patchset is rebased and tested on the spi/for-next (5.7-rc5):
    base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next")

    Link: https://lore.kernel.org/linux-spi/20200508132943.9826-1-Sergey.Semin@baikalelectronics.ru/
    Changelog v2:
    - Rebase on top of the spi repository for-next branch.
    - Move bindings conversion patch to the tail of the series.
    - Move fixes to the head of the series.
    - Apply as many changes as possible to be applied the Generic DMA
    functionality support is added and the spi-dw-mid is moved to the
    spi-dw-dma driver.
    - Discard patch "spi: dw: Fix dma_slave_config used partly uninitialized"
    since the problem has already been fixed.
    - Add new patch "spi: dw: Discard unused void priv pointer".
    - Add new patch "spi: dw: Discard dma_width member of the dw_spi structure".
    n_bytes member of the DW SPI data can be used instead.
    - Build the DMA functionality into the DW APB SSI core if required instead
    of creating a separate kernel module.
    - Use conditional statement instead of the ternary operator in the ref
    clock getter.

    Link: https://lore.kernel.org/linux-spi/20200515104758.6934-1-Sergey.Semin@baikalelectronics.ru/
    Changelog v3:
    - Use spi_delay_exec() method to wait for the DMA operation completion.
    - Explicitly initialize the dw_dma_slave members on stack.
    - Discard the dws->fifo_len utilization in the Tx FIFO DMA threshold
    setting from the patch where we just add the default burst length
    constants.
    - Use min() method to calculate the optimal burst values.
    - Add new patch which moves the spi-dw.c source file to spi-dw-core.c in
    order to preserve the DW APB SSI core driver name.
    - Add commas in the debugfs_reg32 structure initializer and after the last
    entry of the dw_spi_dbgfs_regs array.

    Link: https://lore.kernel.org/linux-spi/20200521012206.14472-1-Sergey.Semin@baikalelectronics.ru
    Changelog v4:
    - Get back ndelay() method to wait for an SPI transfer completion.
    spi_delay_exec() isn't suitable for the atomic context.

    Link: https://lore.kernel.org/linux-spi/20200522000806.7381-1-Sergey.Semin@baikalelectronics.ru
    Changelog v5:
    - Refactor the Tx/Rx DMA-based SPI transfers wait methods.
    - Add a new patch "spi: dw: Set xfer effective_speed_hz".
    - Add a new patch "spi: dw: Return any value retrieved from the
    dma_transfer callback" as a preparation patch before implementing
    the local DMA, Tx SPI and Rx SPI transfers wait methods.
    - Add a new patch "spi: dw: Locally wait for the DMA transactions
    completion", which provides a local DMA transaction complete
    method
    - Create a dedicated patch which adds the Rx-done wait method:
    "spi: dw: Add SPI Rx-done wait method to DMA-based transfer".
    - Add more detailed description of the problems the Tx/Rx-wait
    methods-related patches fix.
    - Wait for the SPI Tx and Rx transfers being finished in the
    mid_spi_dma_transfer() method executed in the task context.
    - Use spi_delay_exec() to wait for the SPI Tx/Rx completion, since now
    the driver calls the wait methods in the kernel thread context.
    - Use SPI_DELAY_UNIT_SCK spi_delay unit for Tx-wait delay, since SPI
    xfer's are now have the effective_speed_hz initialized.
    - Rx-wait for a delay correlated with the APB/SSI synchronous clock
    rate instead of using the SPI bus clock rate.

    Link: https://lore.kernel.org/linux-spi/20200529035915.20790-1-Sergey.Semin@baikalelectronics.ru
    Changelog v6:
    - Provide a more detailed description of the patch:
    2901db35bea1 ("spi: dw: Locally wait for the DMA transfers completion")
    - Calculate the Rx delay with better accuracy by moving 4-multiplication
    to the head of the formulae:
    ns = 4U * NSEC_PER_SEC / dws->max_freq * nents.

    Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
    Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
    Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
    Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
    Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
    Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
    Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
    Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
    Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
    Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
    Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
    Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
    Cc: Arnd Bergmann <arnd@arndb.de>
    Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
    Cc: Feng Tang <feng.tang@intel.com>
    Cc: Rob Herring <robh+dt@kernel.org>
    Cc: linux-mips@vger.kernel.org
    Cc: linux-spi@vger.kernel.org
    Cc: devicetree@vger.kernel.org
    Cc: linux-kernel@vger.kernel.org

    Serge Semin (16):
    spi: dw: Set xfer effective_speed_hz
    spi: dw: Return any value retrieved from the dma_transfer callback
    spi: dw: Locally wait for the DMA transfers completion
    spi: dw: Add SPI Tx-done wait method to DMA-based transfer
    spi: dw: Add SPI Rx-done wait method to DMA-based transfer
    spi: dw: Parameterize the DMA Rx/Tx burst length
    spi: dw: Use DMA max burst to set the request thresholds
    spi: dw: Fix Rx-only DMA transfers
    spi: dw: Add core suffix to the DW APB SSI core source file
    spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
    spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
    spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
    spi: dw: Cleanup generic DW DMA code namings
    spi: dw: Add DMA support to the DW SPI MMIO driver
    spi: dw: Use regset32 DebugFS method to create regdump file
    dt-bindings: spi: Convert DW SPI binding to DT schema

    .../bindings/spi/snps,dw-apb-ssi.txt | 44 --
    .../bindings/spi/snps,dw-apb-ssi.yaml | 127 +++++
    .../devicetree/bindings/spi/spi-dw.txt | 24 -
    drivers/spi/Kconfig | 15 +-
    drivers/spi/Makefile | 5 +-
    drivers/spi/{spi-dw.c => spi-dw-core.c} | 95 ++--
    drivers/spi/spi-dw-dma.c | 482 ++++++++++++++++++
    drivers/spi/spi-dw-mid.c | 382 --------------
    drivers/spi/spi-dw-mmio.c | 4 +
    drivers/spi/spi-dw-pci.c | 50 +-
    drivers/spi/spi-dw.h | 20 +-
    11 files changed, 719 insertions(+), 529 deletions(-)
    delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
    create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
    delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
    rename drivers/spi/{spi-dw.c => spi-dw-core.c} (82%)
    create mode 100644 drivers/spi/spi-dw-dma.c
    delete mode 100644 drivers/spi/spi-dw-mid.c

    --
    2.26.2

    Mark Brown
     
  • 7830c0ef2   spi: dw: add reset control ... Browse Code »

    Add mechanism to get the reset control and deassert it in order to bring
    the IP out of reset.

    Signed-off-by: Liang Jin J
    Signed-off-by: Dinh Nguyen
    Link: https://lore.kernel.org/r/20200529155806.16758-1-dinguyen@kernel.org
    Signed-off-by: Mark Brown

    Dinh Nguyen
     

29 May, 2020

1 commit

  • 0fdad596d   spi: dw: Add DMA support to the DW SPI MMIO driver ... Browse Code »

    Since the common code in the spi-dw-dma.c driver is ready to be used
    by the MMIO driver and now provides a method to generically (on any
    DT or ACPI-based platforms) retrieve the Tx/Rx DMA channel handlers,
    we can use it and a set of the common DW SPI DMA callbacks to enable
    DMA at least for generic "snps,dw-apb-ssi" and "snps,dwc-ssi-1.01a"
    devices.

    Co-developed-by: Georgy Vlasov
    Co-developed-by: Ramil Zaripov
    Signed-off-by: Georgy Vlasov
    Signed-off-by: Ramil Zaripov
    Signed-off-by: Serge Semin
    Reviewed-by: Andy Shevchenko
    Cc: Alexey Malahov
    Cc: Thomas Bogendoerfer
    Cc: Arnd Bergmann
    Cc: Feng Tang
    Cc: Rob Herring
    Cc: linux-mips@vger.kernel.org
    Cc: devicetree@vger.kernel.org
    Link: https://lore.kernel.org/r/20200529131205.31838-15-Sergey.Semin@baikalelectronics.ru
    Signed-off-by: Mark Brown

    Serge Semin
     

16 May, 2020

1 commit

  • 77810d484   spi: dw: Initialize paddr in DW SPI MMIO private data ... Browse Code »

    This field is used only for the DW SPI DMA code initialization, that's
    why there were no problems with it being uninitialized in Dw SPI MMIO
    driver. Since in a further patch we are going to introduce the DW SPI DMA
    support in the MMIO version of the driver, lets set the field with the
    physical address of the DW SPI controller registers region.

    Co-developed-by: Georgy Vlasov
    Co-developed-by: Ramil Zaripov
    Signed-off-by: Georgy Vlasov
    Signed-off-by: Ramil Zaripov
    Signed-off-by: Serge Semin
    Reviewed-by: Andy Shevchenko
    Link: https://lore.kernel.org/r/20200515104758.6934-12-Sergey.Semin@baikalelectronics.ru
    Signed-off-by: Mark Brown

    Serge Semin
     

13 May, 2020

1 commit

12 May, 2020

1 commit

07 May, 2020

1 commit

05 May, 2020

3 commits

  • f42377916   spi: dw: Add support for Intel Keem Bay SPI ... Browse Code »

    Add support for Intel Keem Bay SPI controller, which uses DesignWare
    DWC_ssi core. Bit 31 of CTRLR0 register is added for Keem Bay, to
    configure the device as a master or as a slave serial peripheral.

    Signed-off-by: Wan Ahmad Zainie
    Reviewed-by: Andy Shevchenko
    Link: https://lore.kernel.org/r/20200505130618.554-6-wan.ahmad.zainie.wan.mohamad@intel.com
    Signed-off-by: Mark Brown

    Wan Ahmad Zainie
     
  • e539f435c   spi: dw: Add support for DesignWare DWC_ssi ... Browse Code »

    This patch adds initial support for DesignWare DWC_ssi soft IP. DWC_ssi is
    the enhanced version of DW_apb_ssi, which is currently supported by this
    driver. Their registers are same, but the bit fields of register CTRLR0
    are different.

    DWC_ssi has additional features compared to DW_apb_ssi. Major enhancements
    in DWC_ssi are hyper bus protocol, boot mode support and advanced XIP
    support. DWC_ssi is an AHB slave device, whilst DW_apb_ssi is an APB slave
    device.

    Register offset
    DW_ssi DW_apb_ssi
    CTRLR0 0x00 0x00
    CTRLR1 0x04 0x04
    SSIENR 0x08 0x08
    MWCR 0x0c 0x0c
    SER 0x10 0x10
    BAUDR 0x14 0x14
    TXFTLR 0x18 0x18
    RXFTLR 0x1c 0x1c
    TXFLR 0x20 0x20
    RXFLR 0x24 0x24
    SR 0x28 0x28
    IMR 0x2c 0x2c
    ISR 0x30 0x30
    RISR 0x34 0x34
    TXOICR 0x38 0x38
    RXOICR 0x3c 0x3c
    RXUICR 0x40 0x40
    MSTICR 0x44 0x44
    ICR 0x48 0x48
    DMACR 0x4c 0x4c
    DMATDLR 0x50 0x50
    DMARDLR 0x54 0x54
    IDR 0x58 0x58
    SSI_VERSION_ID 0x5c 0x5c
    DRx (0 to 35) 0x60+i*0x4 0x60+i*0x4
    RX_SAMPLE_DLY 0xf0 0xf0
    SPI_CTRLR0 0xf4 0xf4
    TXD_DRIVE_EDGE 0xf8 0xf8
    XIP_MODE_BITS 0xfc RSVD

    Register configuration - CTRLR0
    DW_ssi DW_apb_ssi
    SPI_HYPERBUS_EN bit[24] NONE
    SPI_FRF bit[23:22] bit[22:21]
    DFS_32 NONE bit[20:16]
    CFS bit[19:16] bit[15:12]
    SSTE bit[14] bit[24]
    SRL bit[13] bit[11]
    SLV_OE bit[12] bit[10]
    TMOD bit[11:10] bit[9:8]
    SCPOL | SPHA bit[9:8] bit[7:6]
    FRF bit[7:6] bit[5:4]
    DFS bit[4:0] bit[3:0]

    The documents used are
    [1] DW_apb_ssi_databook.pdf version 4.01a (2016.10a).
    [2] DWC_ssi_databook.pdf version 1.01a.

    Signed-off-by: Wan Ahmad Zainie
    Reviewed-by: Andy Shevchenko
    Link: https://lore.kernel.org/r/20200505130618.554-4-wan.ahmad.zainie.wan.mohamad@intel.com
    Signed-off-by: Mark Brown

    Wan Ahmad Zainie
     
  • c4eadee21   spi: dw: Add update_cr0() callback to update CTRLR0 ... Browse Code »

    This patch adds update_cr0() callback, in struct dw_spi.

    Existing code that configure register CTRLR0 is moved into a new
    function, dw_spi_update_cr0(), and this will be the default.

    Suggested-by: Andy Shevchenko
    Signed-off-by: Wan Ahmad Zainie
    Reviewed-by: Andy Shevchenko
    Link: https://lore.kernel.org/r/20200505130618.554-3-wan.ahmad.zainie.wan.mohamad@intel.com
    Signed-off-by: Mark Brown

    Wan Ahmad Zainie
     

23 Nov, 2019

1 commit

23 Oct, 2019

1 commit

  • b9fc2d207   spi: dw: Move runtime PM enable/disable from common to platform driver part ... Browse Code »

    After commit 1e6959832510 ("spi: dw: Add basic runtime PM support")
    there is following warning from PCI enumerated DesignWare SPI controller
    during probe:

    dw_spi_pci 0000:00:13.0: Unbalanced pm_runtime_enable!

    Runtime PM is already enabled for PCI devices by the PCI core and doing
    it again in common DW SPI code leads to unbalanced enable calls.

    Fix this by moving the runtime PM enable/disable calls to the platform
    driver part of the driver.

    Cc: Phil Edworthy
    Signed-off-by: Jarkko Nikula
    Reviewed-by: Andy Shevchenko
    Link: https://lore.kernel.org/r/20191018132131.31608-1-jarkko.nikula@linux.intel.com
    Signed-off-by: Mark Brown

    Jarkko Nikula
     

01 Oct, 2019

1 commit

  • 3ade3a37b   spi: dw: Add compatible string for Renesas RZ/N1 SPI Controller ... Browse Code »

    The Renesas RZ/N1 SPI Controller is based on the Synopsys DW SSI, but has
    additional registers for software CS control and DMA. This patch does not
    address the changes required for DMA support, it simply adds the compatible
    string. The CS registers are not needed as Linux can use gpios for the CS
    signals.

    Signed-off-by: Gareth Williams
    Signed-off-by: Phil Edworthy
    Link: https://lore.kernel.org/r/1568793876-9009-5-git-send-email-gareth.williams.jx@renesas.com
    Signed-off-by: Mark Brown

    Phil Edworthy
     

05 Sep, 2019

1 commit

02 Aug, 2019

1 commit

  • 6b8ac10e0   spi: Remove dev_err() usage after platform_get_irq() ... Browse Code »

    We don't need dev_err() messages when platform_get_irq() fails now that
    platform_get_irq() prints an error message itself when something goes
    wrong. Let's remove these prints with a simple semantic patch.

    //
    @@
    expression ret;
    struct platform_device *E;
    @@

    ret =
    (
    platform_get_irq(E, ...)
    |
    platform_get_irq_byname(E, ...)
    );

    if ( \( ret < 0 \| ret

    While we're here, remove braces on if statements that only have one
    statement (manually).

    Cc: Mark Brown
    Cc: linux-spi@vger.kernel.org
    Cc: Greg Kroah-Hartman
    Signed-off-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org
    Signed-off-by: Mark Brown

    Stephen Boyd
     

22 Jul, 2019

2 commits

  • 3da9834d9   spi: dw-mmio: Clock should be shut when error occurs ... Browse Code »

    When optional clock requesting fails, the main clock is still up and running,
    we should shut it down in such caee.

    Fixes: 560ee7e91009 ("spi: dw: Add support for an optional interface clock")
    Cc: Phil Edworthy
    Cc: Gareth Williams
    Signed-off-by: Andy Shevchenko
    Reviewed-by: Gareth Williams
    Link: https://lore.kernel.org/r/20190710114243.30101-1-andriy.shevchenko@linux.intel.com
    Signed-off-by: Mark Brown

    Andy Shevchenko
     
  • 052105021   spi: dw-mmio: Use devm_platform_ioremap_resource() ... Browse Code »

    Use the new helper that wraps the calls to platform_get_resource()
    and devm_ioremap_resource() together.

    Signed-off-by: Andy Shevchenko
    Link: https://lore.kernel.org/r/20190710114230.30047-1-andriy.shevchenko@linux.intel.com
    Signed-off-by: Mark Brown

    Andy Shevchenko
     

05 Jun, 2019

1 commit

  • 75a6faf61   treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422 ... Browse Code »

    Based on 1 normalized pattern(s):

    this program is free software you can redistribute it and or modify
    it under the terms and conditions of the gnu general public license
    version 2 as published by the free software foundation

    extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

    has been chosen to replace the boilerplate/reference in 101 file(s).

    Signed-off-by: Thomas Gleixner
    Reviewed-by: Allison Randal
    Cc: linux-spdx@vger.kernel.org
    Link: https://lkml.kernel.org/r/20190531190113.822954939@linutronix.de
    Signed-off-by: Greg Kroah-Hartman

    Thomas Gleixner
     

21 Mar, 2019

1 commit

  • 560ee7e91   spi: dw: Add support for an optional interface clock ... Browse Code »

    The Synopsys SSI Controller has an interface clock, but most SoCs hide
    this away. However, on some SoCs you need to explicitly enable the
    interface clock in order to access the registers. Therefore, add support
    for an optional interface clock.

    Signed-off-by: Phil Edworthy
    Signed-off-by: Gareth Williams
    Signed-off-by: Mark Brown

    Phil Edworthy
     

09 Jan, 2019

1 commit

  • 9400c41e7   spi: dw: Convert to use CS GPIO descriptors ... Browse Code »

    This converts the DesignWare (dw) SPI master driver to
    use GPIO descriptors for chip select handling.

    This driver has a duplicate DT parser in addition to the
    one in the core, sets up the line as non-asserted and
    relies on the core to drive the GPIOs.

    It is a pretty straight-forward conversion.

    Cc: Talel Shenhar
    Cc: Simon Goldschmidt
    Cc: Alexandre Belloni
    Cc: Linuxarm
    Tested-by: Jay Fang
    Reviewed-by: Alexandre Belloni
    Signed-off-by: Linus Walleij
    Signed-off-by: Mark Brown

    Linus Walleij
     

05 Dec, 2018

1 commit

  • 32215a6c6   spi: dw-mmio: add ACPI support ... Browse Code »

    The Hisilicon Hip08 platform, that uses ACPI, has this controller.
    Let's add ACPI support for DW SPI MMIO-based host.

    The ACPI ID used is "HISI0173" for the Designware SPI controller of
    Hisilicon Hip08 platform.

    Signed-off-by: Jay Fang
    Signed-off-by: Mark Brown

    Jay Fang
     

11 Oct, 2018

1 commit

  • f2d704794   dw: spi: add support for Amazon's Alpine spi controller ... Browse Code »

    Add support for a new devicetree compatible string called
    'amazon,alpine-apb-ssi', which is necessary for the Amazon Alpine spi
    controller. 'amazon,alpine-dw-apb-ssi' is used in the dw spi driver if
    specified in the devicetree. Otherwise, fall back to driver default
    behavior, i.e. original dw IP hw driver behavior.

    Signed-off-by: Talel Shenhar
    Signed-off-by: David Woodhouse
    Signed-off-by: Mark Brown

    Talel Shenhar
     

31 Aug, 2018

1 commit

29 Aug, 2018

1 commit

30 Jul, 2018

1 commit

  • c2c25cc39   spi: dw-mmio: add MSCC Ocelot support ... Browse Code »

    Because the SPI controller deasserts the chip select when the TX fifo is
    empty (which may happen in the middle of a transfer), the CS should be
    handled by linux. Unfortunately, some or all of the first four chip
    selects are not muxable as GPIOs, depending on the SoC.

    There is a way to bitbang those pins by using the SPI boot controller so
    use it to set the chip selects.

    At init time, it is also necessary to give control of the SPI interface to
    the Designware IP.

    Signed-off-by: Alexandre Belloni
    Reviewed-by: Andy Shevchenko
    Signed-off-by: Mark Brown

    Alexandre Belloni
     

19 Apr, 2017

1 commit

  • 400c18e3d   spi: dw: Disable clock after unregistering the host ... Browse Code »

    The dw_mmio driver disables the block clock before unregistering
    the host. The code unregistering the host may access the SPI block
    registers. If register access happens with block clock disabled,
    this may lead to a bus hang. Disable the clock after unregistering
    the host to prevent such situation.

    This bug was observed on Altera Cyclone V SoC.

    Signed-off-by: Marek Vasut
    Cc: Andy Shevchenko
    Cc: Mark Brown
    Signed-off-by: Mark Brown

    Marek Vasut
     

06 Feb, 2016

1 commit

20 Oct, 2015

1 commit

22 Aug, 2015

1 commit

  • c4fe57f76   spi: dw: Allow interface drivers to limit data I/O to word sizes ... Browse Code »

    The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit
    accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit.
    This, unfortunately, breaks data register access on picoXcell, where the
    DW IP needs data register accesses to be word accesses (all other
    accesses appear to be OK).

    This change introduces a new master variable to allow interface drivers
    to specify that 16bit data transfer I/O is required. This change also
    introduces the ability to set this variable via device tree bindings in
    the MMIO interface driver. Both the core and the MMIO interface driver
    default to the current 32bit behaviour.

    Before this change, on a picoXcell pc3x3:
    spi_master spi32766: interrupt_transfer: fifo overrun/underrun
    m25p80 spi32766.0: error -5 reading 9f
    m25p80: probe of spi32766.0 failed with error -5

    After this change:
    m25p80 spi32766.0: m25p40 (512 Kbytes)

    Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses")
    Signed-off-by: Michael van der Westhuizen
    Reviewed-by: Andy Shevchenko
    Signed-off-by: Mark Brown

    Michael van der Westhuizen
     

20 Oct, 2014

1 commit

04 Jul, 2014

1 commit

25 Apr, 2014

1 commit

03 Feb, 2014

1 commit

31 Dec, 2013

2 commits

17 Sep, 2013

1 commit

  • 1e0d191f6   spi: designware: delete premature free_irq ... Browse Code »

    Free_irq is not needed if there has been no request_irq. Free_irq is
    removed from both the probe and remove functions. The correct request_irq
    and free_irq appear to be in the add_host and remove_host functions in
    spi-dw.c.

    A simplified version of the semantic match that finds this problem is as
    follows: (http://coccinelle.lip6.fr/)

    //
    @@
    expression e;
    @@

    *e = platform_get_irq(...);
    ... when != request_irq(e,...)
    *free_irq(e,...)
    //

    Signed-off-by: Julia Lawall
    Signed-off-by: Mark Brown

    Julia Lawall