27 Jul, 2020

1 commit

  • The spi-sun4i driver already has the ability to do large transfers.
    However, the max transfer size reported is still fifo depth - 1.

    Update the max transfer size reported to the max value possible.

    Fixes: 196737912da5 ("spi: sun4i: Allow transfers larger than FIFO size")
    Signed-off-by: Jonathan Liu
    Acked-by: Maxime Ripard
    Link: https://lore.kernel.org/r/20200727072328.510798-1-net147@gmail.com
    Signed-off-by: Mark Brown

    Jonathan Liu
     

05 Sep, 2019

1 commit


02 Aug, 2019

1 commit

  • We don't need dev_err() messages when platform_get_irq() fails now that
    platform_get_irq() prints an error message itself when something goes
    wrong. Let's remove these prints with a simple semantic patch.

    //
    @@
    expression ret;
    struct platform_device *E;
    @@

    ret =
    (
    platform_get_irq(E, ...)
    |
    platform_get_irq_byname(E, ...)
    );

    if ( \( ret < 0 \| ret

    While we're here, remove braces on if statements that only have one
    statement (manually).

    Cc: Mark Brown
    Cc: linux-spi@vger.kernel.org
    Cc: Greg Kroah-Hartman
    Signed-off-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org
    Signed-off-by: Mark Brown

    Stephen Boyd
     

31 May, 2019

1 commit

  • Based on 1 normalized pattern(s):

    this program is free software you can redistribute it and or modify
    it under the terms of the gnu general public license as published by
    the free software foundation either version 2 of the license or at
    your option any later version

    extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-or-later

    has been chosen to replace the boilerplate/reference in 3029 file(s).

    Signed-off-by: Thomas Gleixner
    Reviewed-by: Allison Randal
    Cc: linux-spdx@vger.kernel.org
    Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
    Signed-off-by: Greg Kroah-Hartman

    Thomas Gleixner
     

07 Dec, 2017

1 commit


30 Oct, 2016

1 commit

  • SPI transfers were limited to one FIFO depth, which is 64 bytes.
    This was an artificial limitation, however, as the hardware can handle
    much larger bursts. To accommodate this, we enable the interrupt when
    the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt
    handler. The 3/4 ratio was chosen arbitrarily, with the intention to
    reduce the potential number of interrupts.

    Since the SUN4I_CTL_TP bit is set, the hardware will pause
    transmission whenever the FIFO is full, so there is no risk of losing
    data if we can't service the interrupt in time.

    For the Tx side, enable and use the Tx FIFO 3/4 empty interrupt to
    replenish the FIFO on large SPI bursts. This requires more care in
    when the interrupt is left enabled, as this interrupt will continually
    trigger when the FIFO is less than 1/4 full, even though we
    acknowledge it.

    Signed-off-by: Alexandru Gagniuc
    Acked-by: Maxime Ripard
    Signed-off-by: Olliver Schinagl
    Signed-off-by: Mark Brown

    Alexandru Gagniuc
     

25 Jul, 2016

1 commit


28 Jun, 2016

1 commit

  • The speed limits are unset in the sun4i and sun6i SPI drivers.

    The maximum speed of SPI master is used when maximum speed of SPI slave
    is not specified. Also the __spi_validate function should check that
    transfer speeds do not exceed the master limits.

    The user manual for A10 and A31 specifies maximum
    speed of the SPI clock as 100MHz and minimum as 3kHz.

    Setting the SPI clock to out-of-spec values can lock up the SoC.

    Signed-off-by: Michal Suchanek
    --
    v2:
    new patch
    v3:
    fix constant style
    Signed-off-by: Mark Brown

    Michal Suchanek
     

14 Jun, 2016

3 commits

  • The trasfer timeout is fixed at 1000 ms. Reading a 4Mbyte flash over
    1MHz SPI bus takes way longer than that. Calculate the timeout from the
    actual time the transfer is supposed to take and multiply by 2 for good
    measure.

    Signed-off-by: Michal Suchanek
    Acked-by: Maxime Ripard
    Signed-off-by: Mark Brown
    Cc: stable@vger.kernel.org

    Michal Suchanek
     
  • When testing SPI without DMA I noticed that filling the FIFO on the
    spi controller causes timeout.

    Always leave room for one byte in the FIFO.

    Signed-off-by: Michal Suchanek
    Acked-by: Maxime Ripard
    Signed-off-by: Mark Brown
    Cc: stable@vger.kernel.org

    Michal Suchanek
     
  • The sun4i spi hardware can trasfer at most 63 bytes of data without DMA
    support so report the limitation. Same for sun6i.

    Signed-off-by: Michal Suchanek
    Acked-by: Maxime Ripard
    Signed-off-by: Mark Brown

    Michal Suchanek
     

12 Jan, 2016

1 commit


07 Jan, 2016

1 commit

  • The SPI core calls set_cs before a transfer, but the SUN4I_CTL_CS_MANUAL
    flag is only set in transfer_one. This leads to the following pattern on
    the chip-select line (with runtime power-management on every transfer,
    without it only on the first one):

    activate, deactivate, activate, transfer, deactivate

    Moving the configuration of the SUN4I_CTL_CS_MANUAL flag from transfer_one
    to set_cs removes the double activation.

    Signed-off-by: Marcus Weseloh
    Acked-by: Maxime Ripard
    Signed-off-by: Mark Brown

    Marcus Weseloh
     

19 Nov, 2015

1 commit


20 Oct, 2014

1 commit


15 Apr, 2014

1 commit


04 Mar, 2014

1 commit


23 Feb, 2014

1 commit

  • The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
    controller.

    Unfortunately, this SPI controller, even though quite similar, is significantly
    different from the recently supported A31 SPI controller (different registers
    offset, split/merged registers, etc.). Supporting both controllers in a single
    driver would be unreasonable, hence the addition of a new driver.

    Like its more recent counterpart, it supports DMA, but the driver only does PIO
    until we have a dmaengine driver for this platform.

    Signed-off-by: Maxime Ripard
    Signed-off-by: Mark Brown

    Maxime Ripard