24 Feb, 2020
2 commits
-
[ Upstream commit cea931c25104e6bddc42eb067f58193f355dbdd7 ]
The DM365 platform has a strange quirk (only present when using ancient
u-boot - mainline u-boot v2013.01 and later works fine) where if we
enable the second half of the timer in periodic mode before we do its
initialization - the time won't start flowing and we can't boot.When using more recent u-boot, we can enable the timer, then reinitialize
it and all works fine.To work around this issue only enable clockevents once tim34 is
initialized i.e. move clockevents_config_and_register() below tim34
initialization.Signed-off-by: Bartosz Golaszewski
Signed-off-by: Sekhar Nori
Signed-off-by: Sasha Levin -
[ Upstream commit 2052d032c06761330bca4944bb7858b00960e868 ]
Currently when setup_irq fails the error exit path will leak the
recently allocated timer structure. Originally the code would
throw a panic but a later commit changed the behaviour to return
via the err_iounmap path and hence we now have a memory leak. Fix
this by adding a err_timer_free error path that kfree's timer.Addresses-Coverity: ("Resource Leak")
Fixes: 524a7f08983d ("clocksource/drivers/bcm2835_timer: Convert init function to return error")
Signed-off-by: Colin Ian King
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20191219213246.34437-1-colin.king@canonical.com
Signed-off-by: Sasha Levin
09 Jan, 2020
1 commit
-
commit 9d05c18e8d7de566ff68f221fcae65e78708dd1d upstream.
When enabling ftrace graph tracer, it gets the tracing clock in
ftrace_push_return_trace(). Eventually, it invokes riscv_sched_clock()
to get the clock value. If riscv_sched_clock() isn't marked with
'notrace', it will call ftrace_push_return_trace() and cause infinite
loop.The result of failure as follow:
command: echo function_graph >current_tracer
[ 46.176787] Unable to handle kernel paging request at virtual address ffffffe04fb38c48
[ 46.177309] Oops [#1]
[ 46.177478] Modules linked in:
[ 46.177770] CPU: 0 PID: 256 Comm: $d Not tainted 5.5.0-rc1 #47
[ 46.177981] epc: ffffffe00035e59a ra : ffffffe00035e57e sp : ffffffe03a7569b0
[ 46.178216] gp : ffffffe000d29b90 tp : ffffffe03a756180 t0 : ffffffe03a756968
[ 46.178430] t1 : ffffffe00087f408 t2 : ffffffe03a7569a0 s0 : ffffffe03a7569f0
[ 46.178643] s1 : ffffffe00087f408 a0 : 0000000ac054cda4 a1 : 000000000087f411
[ 46.178856] a2 : 0000000ac054cda4 a3 : 0000000000373ca0 a4 : ffffffe04fb38c48
[ 46.179099] a5 : 00000000153e22a8 a6 : 00000000005522ff a7 : 0000000000000005
[ 46.179338] s2 : ffffffe03a756a90 s3 : ffffffe00032811c s4 : ffffffe03a756a58
[ 46.179570] s5 : ffffffe000d29fe0 s6 : 0000000000000001 s7 : 0000000000000003
[ 46.179809] s8 : 0000000000000003 s9 : 0000000000000002 s10: 0000000000000004
[ 46.180053] s11: 0000000000000000 t3 : 0000003fc815749c t4 : 00000000000efc90
[ 46.180293] t5 : ffffffe000d29658 t6 : 0000000000040000
[ 46.180482] status: 0000000000000100 badaddr: ffffffe04fb38c48 cause: 000000000000000fSigned-off-by: Zong Li
Reviewed-by: Steven Rostedt (VMware)
[paul.walmsley@sifive.com: cleaned up patch description]
Fixes: 92e0d143fdef ("clocksource/drivers/riscv_timer: Provide the sched_clock")
Cc: stable@vger.kernel.org
Signed-off-by: Paul Walmsley
Signed-off-by: Greg Kroah-Hartman
05 Jan, 2020
2 commits
-
[ Upstream commit 4411464d6f8b5e5759637235a6f2b2a85c2be0f1 ]
If a hardware-specific driver does not provide a name, the timer-of core
falls back to device_node.name. Due to generic DT node naming policies,
that name is almost always "timer", and thus doesn't identify the actual
timer used.Fix this by using device_node.full_name instead, which includes the unit
addrees.Example impact on /proc/timer_list:
-Clock Event Device: timer
+Clock Event Device: timer@fcfec400Signed-off-by: Geert Uytterhoeven
Reviewed-by: Rob Herring
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20191016144747.29538-3-geert+renesas@glider.be
Signed-off-by: Sasha Levin -
[ Upstream commit 6e001f6a4cc73cd06fc7b8c633bc4906c33dd8ad ]
asm9260_timer_init misses a check for of_clk_get.
Add a check for it and print errors like other clocksource drivers.Signed-off-by: Chuhong Yuan
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20191016124330.22211-1-hslester96@gmail.com
Signed-off-by: Sasha Levin
05 Nov, 2019
1 commit
-
Pull clockevent fixes from Daniel Lezcano:
- Fix scary messages in sh_mtu2 by using platform_irq_count() helper
function (Geert Uytterhoeven)- Fix double free when using timer-of in the mediatek timer driver
(Fabien Parent)
18 Oct, 2019
1 commit
-
As platform_get_irq_by_name() now prints an error when the interrupt
does not exist, looping over possibly non-existing interrupts causes the
printing of scary messages like:sh_mtu2 fcff0000.timer: IRQ tgi1a not found
sh_mtu2 fcff0000.timer: IRQ tgi2a not foundFix this by using the platform_irq_count() helper, to avoid touching
non-existent interrupts. Limit the returned number of interrupts to the
maximum number of channels currently supported by the driver in a
future-proof way, i.e. using ARRAY_SIZE() instead of a hardcoded number.Fixes: 7723f4c5ecdb8d83 ("driver core: platform: Add an error message to platform_get_irq*()")
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20191016143003.28561-1-geert+renesas@glider.be
16 Oct, 2019
1 commit
-
When timer_of_init fails, it cleans up after itself by undoing
everything it did during the initialization function.mtk_syst_init and mtk_gpt_init both call timer_of_cleanup if
timer_of_init fails. timer_of_cleanup try to release the resource
taken. Since these resources have already been cleaned up by
timer_of_init, we end up getting a few warnings printed:[ 0.001935] WARNING: CPU: 0 PID: 0 at __clk_put+0xe8/0x128
[ 0.002650] Modules linked in:
[ 0.003058] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.19.67+ #1
[ 0.003852] Hardware name: MediaTek MT8183 (DT)
[ 0.004446] pstate: 20400085 (nzCv daIf +PAN -UAO)
[ 0.005073] pc : __clk_put+0xe8/0x128
[ 0.005555] lr : clk_put+0xc/0x14
[ 0.005988] sp : ffffff80090b3ea0
[ 0.006422] x29: ffffff80090b3ea0 x28: 0000000040e20018
[ 0.007121] x27: ffffffc07bfff780 x26: 0000000000000001
[ 0.007819] x25: ffffff80090bda80 x24: ffffff8008ec5828
[ 0.008517] x23: ffffff80090bd000 x22: ffffff8008d8b2e8
[ 0.009216] x21: 0000000000000001 x20: fffffffffffffdfb
[ 0.009914] x19: ffffff8009166180 x18: 00000000002bffa8
[ 0.010612] x17: ffffffc012996980 x16: 0000000000000000
[ 0.011311] x15: ffffffbf004a6800 x14: 3536343038393334
[ 0.012009] x13: 2079726576652073 x12: 7eb9c62c5c38f100
[ 0.012707] x11: ffffff80090b3ba0 x10: ffffff80090b3ba0
[ 0.013405] x9 : 0000000000000004 x8 : 0000000000000040
[ 0.014103] x7 : ffffffc079400270 x6 : 0000000000000000
[ 0.014801] x5 : ffffffc079400248 x4 : 0000000000000000
[ 0.015499] x3 : 0000000000000000 x2 : 0000000000000000
[ 0.016197] x1 : ffffff80091661c0 x0 : fffffffffffffdfb
[ 0.016896] Call trace:
[ 0.017218] __clk_put+0xe8/0x128
[ 0.017654] clk_put+0xc/0x14
[ 0.018048] timer_of_cleanup+0x60/0x7c
[ 0.018551] mtk_syst_init+0x8c/0x9c
[ 0.019020] timer_probe+0x6c/0xe0
[ 0.019469] time_init+0x14/0x44
[ 0.019893] start_kernel+0x2d0/0x46c
[ 0.020378] ---[ end trace 8c1efabea1267649 ]---
[ 0.020982] ------------[ cut here ]------------
[ 0.021586] Trying to vfree() nonexistent vm area ((____ptrval____))
[ 0.022427] WARNING: CPU: 0 PID: 0 at __vunmap+0xd0/0xd8
[ 0.023119] Modules linked in:
[ 0.023524] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.19.67+ #1
[ 0.024498] Hardware name: MediaTek MT8183 (DT)
[ 0.025091] pstate: 60400085 (nZCv daIf +PAN -UAO)
[ 0.025718] pc : __vunmap+0xd0/0xd8
[ 0.026176] lr : __vunmap+0xd0/0xd8
[ 0.026632] sp : ffffff80090b3e90
[ 0.027066] x29: ffffff80090b3e90 x28: 0000000040e20018
[ 0.027764] x27: ffffffc07bfff780 x26: 0000000000000001
[ 0.028462] x25: ffffff80090bda80 x24: ffffff8008ec5828
[ 0.029160] x23: ffffff80090bd000 x22: ffffff8008d8b2e8
[ 0.029858] x21: 0000000000000000 x20: 0000000000000000
[ 0.030556] x19: ffffff800800d000 x18: 00000000002bffa8
[ 0.031254] x17: 0000000000000000 x16: 0000000000000000
[ 0.031952] x15: ffffffbf004a6800 x14: 3536343038393334
[ 0.032651] x13: 2079726576652073 x12: 7eb9c62c5c38f100
[ 0.033349] x11: ffffff80090b3b40 x10: ffffff80090b3b40
[ 0.034047] x9 : 0000000000000005 x8 : 5f5f6c6176727470
[ 0.034745] x7 : 5f5f5f5f28282061 x6 : ffffff80091c86ef
[ 0.035443] x5 : ffffff800852b690 x4 : 0000000000000000
[ 0.036141] x3 : 0000000000000002 x2 : 0000000000000002
[ 0.036839] x1 : 7eb9c62c5c38f100 x0 : 7eb9c62c5c38f100
[ 0.037536] Call trace:
[ 0.037859] __vunmap+0xd0/0xd8
[ 0.038271] vunmap+0x24/0x30
[ 0.038664] __iounmap+0x2c/0x34
[ 0.039088] timer_of_cleanup+0x70/0x7c
[ 0.039591] mtk_syst_init+0x8c/0x9c
[ 0.040060] timer_probe+0x6c/0xe0
[ 0.040507] time_init+0x14/0x44
[ 0.040932] start_kernel+0x2d0/0x46cThis commit remove the calls to timer_of_cleanup when timer_of_init
fails since it is unnecessary and actually cause warnings to be printed.Fixes: a0858f937960 ("mediatek: Convert the driver to timer-of")
Signed-off-by: Fabien Parent
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/linux-arm-kernel/20190919191315.25190-1-fparent@baylibre.com/
03 Oct, 2019
1 commit
-
Randy Dunlap reports on the sparse list that sparse warns about this
expression:of_irq->percpu ? free_percpu_irq(of_irq->irq, clkevt) :
free_irq(of_irq->irq, clkevt);and honestly, sparse is correct to warn. The return type of
free_percpu_irq() is 'void', while free_irq() returns a 'const void *'
that is the devname argument passed in to the request_irq().You can't mix a void type with a non-void types in a conditional
expression according to the C standard. It so happens that gcc seems to
accept it - and the resulting type of the expression is void - but
there's really no reason for the kernel to have this kind of
non-standard expression with no real upside.The natural way to write that expression is with an if-statement:
if (of_irq->percpu)
free_percpu_irq(of_irq->irq, clkevt);
else
free_irq(of_irq->irq, clkevt);which is more legible anyway.
I'm not sure why that timer-of code seems to have this odd pattern. It
does the same at allocation time, but at least there the types match,
and it makes sense as an expression.Reported-by: Randy Dunlap
Signed-off-by: Linus Torvalds
23 Sep, 2019
1 commit
-
Pull MIPS updates from Paul Burton:
"Main MIPS changes:- boot_mem_map is removed, providing a nice cleanup made possible by
the recent removal of bootmem.- Some fixes to atomics, in general providing compiler barriers for
smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs
or MIPS32 systems using cmpxchg64().- Conversion to the new generic VDSO infrastructure courtesy of
Vincenzo Frascino.- Removal of undefined behavior in set_io_port_base(), fixing the
behavior of some MIPS kernel configurations when built with recent
clang versions.- Initial MIPS32 huge page support, functional on at least Ingenic
SoCs.- pte_special() is now supported for some configurations, allowing
among other things generic fast GUP to be used.- Miscellaneous fixes & cleanups.
And platform specific changes:
- Major improvements to Ingenic SoC support from Paul Cercueil,
mostly enabled by the inclusion of the new TCU (timer-counter unit)
drivers he's spent a very patient year or so working on. Plus some
fixes for X1000 SoCs from Zhou Yanjie.- Netgear R6200 v1 systems are now supported by the bcm47xx platform.
- DT updates for BMIPS, Lantiq & Microsemi Ocelot systems"
* tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (89 commits)
MIPS: Detect bad _PFN_SHIFT values
MIPS: Disable pte_special() for MIPS32 with RiXi
MIPS: ralink: deactivate PCI support for SOC_MT7621
mips: compat: vdso: Use legacy syscalls as fallback
MIPS: Drop Loongson _CACHE_* definitions
MIPS: tlbex: Remove cpu_has_local_ebase
MIPS: tlbex: Simplify r3k check
MIPS: Select R3k-style TLB in Kconfig
MIPS: PCI: refactor ioc3 special handling
mips: remove ioremap_cachable
mips/atomic: Fix smp_mb__{before,after}_atomic()
mips/atomic: Fix loongson_llsc_mb() wreckage
mips/atomic: Fix cmpxchg64 barriers
MIPS: Octeon: remove duplicated include from dma-octeon.c
firmware: bcm47xx_nvram: Allow COMPILE_TEST
firmware: bcm47xx_nvram: Correct size_t printf format
MIPS: Treat Loongson Extensions as ASEs
MIPS: Remove dev_err() usage after platform_get_irq()
MIPS: dts: mscc: describe the PTP ready interrupt
MIPS: dts: mscc: describe the PTP register range
...
18 Sep, 2019
1 commit
-
Pull core timer updates from Thomas Gleixner:
"Timers and timekeeping updates:- A large overhaul of the posix CPU timer code which is a preparation
for moving the CPU timer expiry out into task work so it can be
properly accounted on the task/process.An update to the bogus permission checks will come later during the
merge window as feedback was not complete before heading of for
travel.- Switch the timerqueue code to use cached rbtrees and get rid of the
homebrewn caching of the leftmost node.- Consolidate hrtimer_init() + hrtimer_init_sleeper() calls into a
single function- Implement the separation of hrtimers to be forced to expire in hard
interrupt context even when PREEMPT_RT is enabled and mark the
affected timers accordingly.- Implement a mechanism for hrtimers and the timer wheel to protect
RT against priority inversion and live lock issues when a (hr)timer
which should be canceled is currently executing the callback.
Instead of infinitely spinning, the task which tries to cancel the
timer blocks on a per cpu base expiry lock which is held and
released by the (hr)timer expiry code.- Enable the Hyper-V TSC page based sched_clock for Hyper-V guests
resulting in faster access to timekeeping functions.- Updates to various clocksource/clockevent drivers and their device
tree bindings.- The usual small improvements all over the place"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (101 commits)
posix-cpu-timers: Fix permission check regression
posix-cpu-timers: Always clear head pointer on dequeue
hrtimer: Add a missing bracket and hide `migration_base' on !SMP
posix-cpu-timers: Make expiry_active check actually work correctly
posix-timers: Unbreak CONFIG_POSIX_TIMERS=n build
tick: Mark sched_timer to expire in hard interrupt context
hrtimer: Add kernel doc annotation for HRTIMER_MODE_HARD
x86/hyperv: Hide pv_ops access for CONFIG_PARAVIRT=n
posix-cpu-timers: Utilize timerqueue for storage
posix-cpu-timers: Move state tracking to struct posix_cputimers
posix-cpu-timers: Deduplicate rlimit handling
posix-cpu-timers: Remove pointless comparisons
posix-cpu-timers: Get rid of 64bit divisions
posix-cpu-timers: Consolidate timer expiry further
posix-cpu-timers: Get rid of zero checks
rlimit: Rewrite non-sensical RLIMIT_CPU comment
posix-cpu-timers: Respect INFINITY for hard RTTIME limit
posix-cpu-timers: Switch thread group sampling to array
posix-cpu-timers: Restructure expiry array
posix-cpu-timers: Remove cputime_expires
...
05 Sep, 2019
1 commit
-
If we just use the CSRs that these map to directly the code is simpler
and doesn't require extra inline assembly code. Also fix up the top-level
comment in timer-riscv.c to not talk about the cycle count or mention
details of the clocksource interface, of which this file is just a
consumer.Signed-off-by: Christoph Hellwig
Reviewed-by: Atish Patra
Signed-off-by: Paul Walmsley
27 Aug, 2019
10 commits
-
Update the CMT driver to mark "renesas,cmt-48" as deprecated.
Instead of documenting a theoretical hardware device based on current software
support level, define DT bindings top-down based on available data sheet
information and make use of part numbers in the DT compat string.In case of the only in-tree users r8a7740 and sh73a0 the compat strings
"renesas,r8a7740-cmt1" and "renesas,sh73a0-cmt1" may be used instead.Signed-off-by: Magnus Damm
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Daniel Lezcano -
Add SoC-specific matching for CMT1 on r8a7740 and sh73a0.
This allows us to move away from the old DT bindings such as
- "renesas,cmt-48-sh73a0"
- "renesas,cmt-48-r8a7740"
- "renesas,cmt-48"
in favour for the now commonly used format "renesas,-"Signed-off-by: Magnus Damm
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Daniel Lezcano -
Deferred probe is an expected return value on many platforms and so
there's no need to output a warning that may potentially confuse users.Signed-off-by: Jon Hunter
Signed-off-by: Daniel Lezcano -
Deferred probe is an expected return value for clk_get() on many
platforms. The driver deals with it properly, so there's no need
to output a warning that may potentially confuse users.Signed-off-by: Jon Hunter
Signed-off-by: Daniel Lezcano -
NPCM7XX_Tx_OPER GENMASK bits are wrong, fix them.
Hopefully the NPCM7XX_REG_TICR0 register reset value of those bits was 0,
so it did not cause an issue.The function npcm7xx_timer_oneshot() reads the register
NPCM7XX_REG_TCSR0, modifies it and then reads it again overwriting the
previous changes. Remove the extra read which is pointless.The function npcm7xx_timer_periodic() is correct but the code writes
to the NPCM7XX_REG_TICR0 register while it is dealing with the
NPCM7XX_REG_TCSR0 register, that is confusing. Separate the write to
the registers in the code for the sake of clarity.Fixes: 1c00289ecd12 ("clocksource/drivers/npcm: Add NPCM7xx timer driver")
Signed-off-by: Avi Fishman
Signed-off-by: Daniel Lezcano -
Use the DIV_ROUND_CLOSEST() helper instead of open-coding the same
operation.Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
Signed-off-by: Daniel Lezcano -
The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.Signed-off-by: Anson Huang
Signed-off-by: Daniel Lezcano -
Implement and register delay timer to allow get_cycles() to work properly.
Signed-off-by: Alexandre Belloni
Signed-off-by: Daniel Lezcano -
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.Signed-off-by: Maxime Ripard
Acked-by: Daniel Lezcano
Signed-off-by: Daniel Lezcano -
We don't need dev_err() messages when platform_get_irq() fails now that
platform_get_irq() prints an error message itself when something goes
wrong. Let's remove these prints with a simple semantic patch.//
@@
expression ret;
struct platform_device *E;
@@ret =
(
platform_get_irq(E, ...)
|
platform_get_irq_byname(E, ...)
);if ( \( ret < 0 \| ret
While we're here, remove braces on if statements that only have one
statement (manually).Cc: Greg Kroah-Hartman
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Signed-off-by: Stephen Boyd
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Daniel Lezcano
23 Aug, 2019
3 commits
-
There is no particular reason to not enable TSC page clocksource on
32-bit. mul_u64_u64_shr() is available and despite the increased
computational complexity (compared to 64bit) TSC page is still a huge win
compared to MSR-based clocksource.In-kernel reads:
MSR based clocksource: 3361 cycles
TSC page clocksource: 49 cyclesReads from userspace (utilizing vDSO in case of TSC page):
MSR based clocksource: 5664 cycles
TSC page clocksource: 131 cyclesEnabling TSC page on 32bits allows to get rid of CONFIG_HYPERV_TSCPAGE as
it is now not any different from CONFIG_HYPERV_TIMER.Signed-off-by: Vitaly Kuznetsov
Signed-off-by: Thomas Gleixner
Reviewed-by: Michael Kelley
Link: https://lkml.kernel.org/r/20190822083630.17059-1-vkuznets@redhat.com -
Hyper-V guests use the default native_sched_clock() in
pv_ops.time.sched_clock on x86. But native_sched_clock() directly uses the
raw TSC value, which can be discontinuous in a Hyper-V VM.Add the generic hv_setup_sched_clock() to set the sched clock function
appropriately. On x86, this sets pv_ops.time.sched_clock to read the
Hyper-V reference TSC value that is scaled and adjusted to be continuous.Also move the Hyper-V reference TSC initialization much earlier in the boot
process so no discontinuity is observed when pv_ops.time.sched_clock
calculates its offset.[ tglx: Folded build fix ]
Signed-off-by: Tianyu Lan
Signed-off-by: Thomas Gleixner
Reviewed-by: Michael Kelley
Link: https://lkml.kernel.org/r/20190814123216.32245-3-Tianyu.Lan@microsoft.com -
Prepare to add Hyper-V sched clock callback and move Hyper-V Reference TSC
initialization much earlier in the boot process. Earlier initialization is
needed so that it happens while the timestamp value is still 0 and no
discontinuity in the timestamp will occur when pv_ops.time.sched_clock
calculates its offset.The earlier initialization requires that the Hyper-V TSC page be allocated
statically instead of with vmalloc(), so fixup the references to the TSC
page and the method of getting its physical address.Signed-off-by: Tianyu Lan
Signed-off-by: Thomas Gleixner
Acked-by: Daniel Lezcano
Link: https://lkml.kernel.org/r/20190814123216.32245-2-Tianyu.Lan@microsoft.com
09 Aug, 2019
1 commit
-
This driver handles the TCU (Timer Counter Unit) present on the Ingenic
JZ47xx SoCs, and provides the kernel with a system timer, a clocksource
and a sched_clock.Signed-off-by: Paul Cercueil
Tested-by: Mathieu Malaterre
Tested-by: Artur Rojek
Reviewed-by: Thomas Gleixner
Signed-off-by: Paul Burton
Cc: Ralf Baechle
Cc: James Hogan
Cc: Jonathan Corbet
Cc: Lee Jones
Cc: Arnd Bergmann
Cc: Daniel Lezcano
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: od@zcrc.me
07 Aug, 2019
1 commit
-
There is only one clocksource in RISC-V. The boot cpu initializes
that clocksource. No need to keep a percpu data structure.Signed-off-by: Atish Patra
Signed-off-by: Paul Walmsley
Acked-by: Daniel Lezcano
10 Jul, 2019
1 commit
-
Arguments are supposed to be ordered high then low.
Signed-off-by: Joe Perches
Signed-off-by: Thomas Gleixner
Link: https://lkml.kernel.org/r/d6a9d49c9837d38816b71d783f5aed7235e8ca94.1562734889.git.joe@perches.com
03 Jul, 2019
3 commits
-
Continue consolidating Hyper-V clock and timer code into an ISA
independent Hyper-V clocksource driver.Move the existing clocksource code under drivers/hv and arch/x86 to the new
clocksource driver while separating out the ISA dependencies. Update
Hyper-V initialization to call initialization and cleanup routines since
the Hyper-V synthetic clock is not independently enumerated in ACPI.Update Hyper-V clocksource users in KVM and VDSO to get definitions from
the new include file.No behavior is changed and no new functionality is added.
Suggested-by: Marc Zyngier
Signed-off-by: Michael Kelley
Signed-off-by: Thomas Gleixner
Reviewed-by: Vitaly Kuznetsov
Cc: "bp@alien8.de"
Cc: "will.deacon@arm.com"
Cc: "catalin.marinas@arm.com"
Cc: "mark.rutland@arm.com"
Cc: "linux-arm-kernel@lists.infradead.org"
Cc: "gregkh@linuxfoundation.org"
Cc: "linux-hyperv@vger.kernel.org"
Cc: "olaf@aepfle.de"
Cc: "apw@canonical.com"
Cc: "jasowang@redhat.com"
Cc: "marcelo.cerri@canonical.com"
Cc: Sunil Muthuswamy
Cc: KY Srinivasan
Cc: "sashal@kernel.org"
Cc: "vincenzo.frascino@arm.com"
Cc: "linux-arch@vger.kernel.org"
Cc: "linux-mips@vger.kernel.org"
Cc: "linux-kselftest@vger.kernel.org"
Cc: "arnd@arndb.de"
Cc: "linux@armlinux.org.uk"
Cc: "ralf@linux-mips.org"
Cc: "paul.burton@mips.com"
Cc: "daniel.lezcano@linaro.org"
Cc: "salyzyn@android.com"
Cc: "pcc@google.com"
Cc: "shuah@kernel.org"
Cc: "0x7f454c46@gmail.com"
Cc: "linux@rasmusvillemoes.dk"
Cc: "huw@codeweavers.com"
Cc: "sfr@canb.auug.org.au"
Cc: "pbonzini@redhat.com"
Cc: "rkrcmar@redhat.com"
Cc: "kvm@vger.kernel.org"
Link: https://lkml.kernel.org/r/1561955054-1838-3-git-send-email-mikelley@microsoft.com -
Hyper-V clock/timer code and data structures are currently mixed
in with other code in the ISA independent drivers/hv directory as
well as the ISA dependent Hyper-V code under arch/x86.Consolidate this code and data structures into a Hyper-V clocksource driver
to better follow the Linux model. In doing so, separate out the ISA
dependent portions so the new clocksource driver works for x86 and for the
in-process Hyper-V on ARM64 code.To start, move the existing clockevents code to create the new clocksource
driver. Update the VMbus driver to call initialization and cleanup routines
since the Hyper-V synthetic timers are not independently enumerated in
ACPI.No behavior is changed and no new functionality is added.
Suggested-by: Marc Zyngier
Signed-off-by: Michael Kelley
Signed-off-by: Thomas Gleixner
Reviewed-by: Vitaly Kuznetsov
Cc: "bp@alien8.de"
Cc: "will.deacon@arm.com"
Cc: "catalin.marinas@arm.com"
Cc: "mark.rutland@arm.com"
Cc: "linux-arm-kernel@lists.infradead.org"
Cc: "gregkh@linuxfoundation.org"
Cc: "linux-hyperv@vger.kernel.org"
Cc: "olaf@aepfle.de"
Cc: "apw@canonical.com"
Cc: "jasowang@redhat.com"
Cc: "marcelo.cerri@canonical.com"
Cc: Sunil Muthuswamy
Cc: KY Srinivasan
Cc: "sashal@kernel.org"
Cc: "vincenzo.frascino@arm.com"
Cc: "linux-arch@vger.kernel.org"
Cc: "linux-mips@vger.kernel.org"
Cc: "linux-kselftest@vger.kernel.org"
Cc: "arnd@arndb.de"
Cc: "linux@armlinux.org.uk"
Cc: "ralf@linux-mips.org"
Cc: "paul.burton@mips.com"
Cc: "daniel.lezcano@linaro.org"
Cc: "salyzyn@android.com"
Cc: "pcc@google.com"
Cc: "shuah@kernel.org"
Cc: "0x7f454c46@gmail.com"
Cc: "linux@rasmusvillemoes.dk"
Cc: "huw@codeweavers.com"
Cc: "sfr@canb.auug.org.au"
Cc: "pbonzini@redhat.com"
Cc: "rkrcmar@redhat.com"
Cc: "kvm@vger.kernel.org"
Link: https://lkml.kernel.org/r/1561955054-1838-2-git-send-email-mikelley@microsoft.com -
so the hyper-v clocksource update can be applied.
26 Jun, 2019
9 commits
-
Extend the davinci-timer driver to also register a clock source.
Signed-off-by: Bartosz Golaszewski
Signed-off-by: Daniel Lezcano -
Currently the clocksource and clockevent support for davinci platforms
lives in mach-davinci. It hard-codes many things, uses global variables,
implements functionalities unused by any platform and has code fragments
scattered across many (often unrelated) files.Implement a new, modern and simplified timer driver and put it into
drivers/clocksource. We still need to support legacy board files so
export a config structure and a function that allows machine code to
register the timer.The timer we're using is 64-bit but can be programmed in dual 32-bit
mode (both chained and unchained).On all davinci SoCs except for da830 we're using both halves. Lower half
for clockevents and upper half for clocksource. On da830 we're using the
lower half for both with the help of a compare register.This patch contains the core code and support for clockevent. The
clocksource code will be included in a subsequent patch.Signed-off-by: Bartosz Golaszewski
Signed-off-by: Daniel Lezcano -
Tegra's timer has 29 bits for the counter and for the "load" register
which sets counter to a load-value. The counter's value is lower than
the actual value by 1 because it starts to decrement after one tick,
hence the maximum number of ticks that hardware can handle equals to
29 bits + 1.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
Tegra's timer uses n+1 scheme for the counter, i.e. timer will fire after
one tick if 0 is loaded. The minimum and maximum numbers of oneshot ticks
are defined by clockevents_config_and_register(min, max) invocation and
the min value is set to 1 tick. Hence "cycles" value can't ever be 0,
unless it's a bug in clocksource core.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
We're adjusting the timer's base for each per-CPU timer to point to the
actual start of the timer since device-tree defines a compound registers
range that includes all of the timers. In this case the original base
need to be restore before calling iounmap to unmap the proper address.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
Convert all 1MHz literals to a verbose constant for better readability.
Suggested-by: Daniel Lezcano
Acked-by: Jon Hunter
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
There is no need to cast void because kernel allows to do that without
a warning message from a compiler.Acked-by: Jon Hunter
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
The of_clk structure has a period field that is set up initially by
timer_of_clk_init(), that period value need to be adjusted for a case of
TIMER1-9 that are running at a fixed rate that doesn't match the clock's
rate. Note that the period value is currently used only by some of the
clocksource drivers internally and hence this is just a minor cleanup
change that doesn't fix anything.Signed-off-by: Dmitry Osipenko
Acked-by: Jon Hunter
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano -
It was left unnoticed by accident, which means that the code could be
cleaned up a tad more.Acked-by: Jon Hunter
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
Signed-off-by: Daniel Lezcano
