08 Jun, 2017
40 commits
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imx7ulp non core register mapping is similar with imx7d, and the
initialization is the same, but lacks of USB charger detection support.Signed-off-by: Peter Chen
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At v4.1 kernel, we can't get cable type at notifier, but at
extcon-usb-gpio.c notifies both VBUS and ID event, we had to
do special handling for ID event, and omit VBUS event. Current
implementation only supports ID extcon event.If wakeup event occurs by extcon, it needs to call ci_irq again since the
first ci_irq calling at extcon notifier only wakes up controller, but
do noop for event handling.Signed-off-by: Peter Chen
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At imx7ulp, the USB related analog register is located in PHY register
region too, so we need to control PLL at PHY driver directly.Signed-off-by: Peter Chen
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The two extcon notifiers are almost the same except for the
variable name for the cable structure and the id notifier inverts
the cable->state logic. Make it the same and replace two
functions with one to save some lines. This also makes it so that
the id cable state is true when the id pin is pulled low, so we
change the name of ->state to ->connected to properly reflect
that we're interested in the cable being connected.Cc: Peter Chen
Cc: Greg Kroah-Hartman
Cc: "Ivan T. Ivanov"
Signed-off-by: Stephen Boyd
Signed-off-by: Peter Chen -
We're currently emulating the vbus and id interrupts in the OTGSC
read API, but we also need to make sure that if we're handling
the events with extcon that we don't enable the interrupts for
those events in the hardware. Therefore, properly emulate this
register if we're using extcon, but don't enable the interrupts.
This allows me to get my cable connect/disconnect working
properly without getting spurious interrupts on my device that
uses an extcon for these two events.Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Cc: "Ivan T. Ivanov"
Fixes: 3ecb3e09b042 ("usb: chipidea: Use extcon framework for VBUS and ID detect")
Signed-off-by: Stephen Boyd
Signed-off-by: Peter Chen -
With the id and vbus detection done via extcon we need to make
sure we poll the status of OTGSC properly by considering what the
extcon is saying, and not just what the register is saying. Let's
move this hw_wait_reg() function to the only place it's used and
simplify it for polling the OTGSC register. Then we can make
certain we only use the hw_read_otgsc() API to read OTGSC, which
will make sure we properly handle extcon events.Acked-by: Peter Chen
Cc: Greg Kroah-Hartman
Cc: "Ivan T. Ivanov"
Fixes: 3ecb3e09b042 ("usb: chipidea: Use extcon framework for VBUS and ID detect")
Signed-off-by: Stephen Boyd
Signed-off-by: Peter Chen -
This patch fixes below build warning:
CC arch/arm/mach-imx/clk-imx7ulp.o
LD init/built-in.o
arch/arm/mach-imx/clk-imx7ulp.c:42:20: warning: 'cm4_periph_plat_sels' defined but not used [-Wunused-variable]
LD arch/arm/mach-imx/built-in.o
CC kernel/module.o
GZIP kernel/config_data.gzSigned-off-by: Anson Huang
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add pf1550 regulator rpmsg driver to control pf1550 on the m4 side
by rpmsg.Signed-off-by: Robin Gong
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A null dereference or Oops exception might occurs when reading at once the
whole content of an spi-nor of big enough size that requires an scatterlist
table that does not fit into one single page.The spi_map_buf function is ignoring the chained sg case by dereferenceing
the scatterlist elements in an array fashion. This wrongly assumes that
the allocation of the scatterlist elements are contiguous. This is true as
long as the scatterlist table fits within a PAGE_SIZE. However, for
allocation where the scatter table is bigger than that, the pages allocated
by sg_alloc might not be contigous.The sg table can be properly walked by sg_next instead of using an array.
Signed-off-by: Juan Gutierrez
Signed-off-by: Mark Brown -
SAI in M4 domain, and the clock used by SAI is in M4 domain
Signed-off-by: Shengjiu Wang
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Add system reboot for i.MX7ULP. As there is no other way to reboot the
system, so use wdog restart handler to trigger the system reboot.Signed-off-by: Bai Ping
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This patch adds lpi2c bus driver to support new i.MX products
which use lpi2c instead of the old imx i2c.The lpi2c can continue operating in stop mode when an appropriate
clock is available. It is also designed for low CPU overhead with
DMA offloading of FIFO register accesses.Signed-off-by: Gao Pan
Reviewed-by: Fugang Duan
Reviewed-by: Vladimir Zapolskiy
Signed-off-by: Wolfram Sang -
- correct DMAMUX enable bit.
- correct mapping the DMAMUX source and slot.Signed-off-by: Fugang Duan
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Add fw/nv path parse from dts support to support multiple modules
with build in.Signed-off-by: Fugang Duan
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Calculate the rela count for the case that eDMA stop after get eeop signal.
Signed-off-by: Fugang Duan
Signed-off-by: Robin Gong -
Updated the edma driver to support edma2 on ULP1.
Signed-off-by: Shenwei Wang
Signed-off-by: Robin Gong -
When resuming from VLLS mode, the wdog will be reset, the first we configure
the wdog, an initial timeout value should be write into the TOVAL register,
otherwise, the wdog will not be initialized successfully.Signed-off-by: Bai Ping
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Add gpio port control clocks, and add them to init table.
If the gpio clock is controlled by gpio driver, the watchdog
reset will occur due to unknown reason, we need to debug it
if we need driver to control its clocks.Signed-off-by: Peter Chen
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On i.MX7ULP, the IOMUXC PAD register has IBE and OBE bit to control
the input/output buffer if a PIN wants to use as GPIO function.Additonally, on i.MX7ULP, the MUX reg and CONFIG reg is shared in one
register and the GPIO function select in the MUX is not index zero as
on I.MX6 SOC, add support in code for i.MX7ULP GPIO function.Signed-off-by: Bai Ping
Signed-off-by: Fugang Duan
Signed-off-by: Peter Chen -
Add direction set for mx7ulp.
Signed-off-by: Fugang Duan
Signed-off-by: Peter Chen -
Add watchdog driver for i.MX7ULP.
Signed-off-by: Bai Ping
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Improve the fractional divider calculation accuracy use
continued fraction method.Signed-off-by: Bai Ping
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On i.MX7ULP, there are options to select SPLL or SPLL PFD
as SPLL output clock SPLL_SEL, so the SPLL option for
sys_sel mux should be from SPLL_SEL, NOT from SPLL directly.Previous:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 2 2 531648000 0
sys_sel 1 1 531648000 0
core_div 2 2 531648000 0
plat_div 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 1 1 503666526 0
spll_pfd_sel 0 0 503666526 0
spll_sel 0 0 503666526 0
After fixed:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 2 2 503666526 0
spll_pfd_sel 1 1 503666526 0
spll_sel 1 1 503666526 0
sys_sel 1 1 503666526 0
core_div 1 1 503666526 0
plat_div 1 1 503666526 0CORE_DIV clock will be enabled automatically when PLAT_DIV
is enabled, so we can skip it in clks_init_on.Now that sys_sel clock tree is correct, no need to have SPLL_PFD0
in clks_init_on, as it will be enabled automatically because of
PLAT_DIV.Signed-off-by: Anson Huang
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change parent clock to pll3_pfd2 and calculate out a desired pixel clock
rate. This patch fixed the following warning.
"imx_epdc_v2_fb 20f4000.epdc: Unable to get an accurate EPDC pix clkdesired = 40000000, actual = 63529412"Signed-off-by: Robby Cai
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When enter VLLS mode, DRAM is in self-refresh, NVCC_DRAM_SW
can be off to save power.As the static io-map formula is no longer feasible on i.MX7ULP,
here we change it to ioremap for creating iram tlb.Remove the physical module base address in pm_info structure
to save iram space.Signed-off-by: Anson Huang
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Support i.MX6SLL OTP.
There are 4 works in bank7/bank8.
When read, use address offset.
When prog, use bank/index, note that bank7/bank8 we treat
them a single bank when prog.Tested GP41 and GP31 read/write on eng sample chip.
Signed-off-by: Peng Fan
(cherry picked from commit f8698b66fcbec7409b738a4c5b05ba87f0342cf8) -
As TPM default clock parent is changed to OSC which is 24MHz,
to keep its frequency as 3MHz, need to update its divider
from 16 to 8.Signed-off-by: Anson Huang
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The PCC clock bit field definition is as below:
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5So previous clock driver sets PCC clock parent to
start from index value 1 by setting CLK_MUX_INDEX_ONE
flag, however it has an issue of getting clock parent
when the register field value is 0, below is the clk
get parent code from clk driver:if (val && (mux->flags & CLK_MUX_INDEX_BIT))
val = ffs(val) - 1;if (val && (mux->flags & CLK_MUX_INDEX_ONE))
val--;The val is 0, so the parent will be returned as first
clock parent in PCC register field which is 001b,
that will cause setting clk parent fail when the
reset value is 0 and we try to set clk parent to
option 1, as clk driver thinks current clk parent
is same as the new parent.Fix this issue by adding dummy clock as option0, ths
clk gate is controlled by bit 30, so it would NOT impact
gating function.Signed-off-by: Anson Huang
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Correct a macro definition in mxsfb.c
In framebuffer driver, a macro define LCDIF_CTRL2n register bits[23-21] value
is 0x3, but according to reference manual, it should be 0x4, so correct it.Signed-off-by: Guoniu.Zhou
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On some SoCs such as i.MX7ULP, there is no busfreq
driver, but cpuidle has some levels which may disable
system/bus clocks, so need to add pm_qos to prevent
cpuidle from entering low level idles and make sure
system/bus clocks are enabled when usdhc is active.Signed-off-by: Anson Huang
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On i.MX7ULP, IOMUX's mux and pad config are in
same register, but mux field is different, add
support in pinctrl driver.Signed-off-by: Anson Huang
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Add property to define mux register mask bits when SHARE_MUX_CONF_REG
flag is added.Signed-off-by: Fugang Duan
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Add support for imx7ulp iomux controller.
Signed-off-by: Fugang Duan
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Add i.MX7ULP clock driver.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Fancy Fang -
Add below new clock types to support new SoC:
composite clk;
frac-divider;
pfdv2;
pllv4.These clock types are for i.MX7ULP and maybe
following SoCs.Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
[Octavian: fix build warning by using u64 in do_div ops]
Signed-off-by: Octavian Purdila -
Add i.MX TPM support for clock source.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping -
When usdhc driver remove, also need to release bus frequency.
Signed-off-by: Haibo Chen
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Add the support for a CT36X based touchscreens using
the CT36X controller and i2c touchscreen interface.Signed-off-by: Alejandro Lozano
Signed-off-by: Juan Gutierrez
Signed-off-by: Alejandro Sierra -
When suspend usdhc, it will access usdhc register. So usdhc clock
should be enabled, otherwise the access usdhc register will return
error or cause system.Take this into consideration, if system enable a usdhc and do not
connect any SD/SDIO/MMC card, after system boot up, this usdhc
will do runtime suspend, and close all usdhc clock. At this time,
if suspend the system, due to no card persent, usdhc runtime resume
will not be called. So usdhc clock still closed, then in suspend,
once access usdhc register, system hung or bus error return.This patch make sure usdhc clock always enabled while doing usdhc
suspend.Signed-off-by: Haibo Chen
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Add one new regulator events macro 'REGULATOR_EVENT_AFT_DO_ENABLE'.
1.8v of imx7d pcie phy, should be turned on after
the 1p0d(1.0v) of pcie phy is turned on.Signed-off-by: Richard Zhu