17 Oct, 2024
1 commit
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According the latest RM, the ND frequency of MEDIA AXI should be 333M
for i.MX91.Signed-off-by: Pengfei Li
Reviewed-by: Ye Li
16 Oct, 2024
1 commit
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There are two problems when switch to ND mode with no_od_mode enabled
like iMX91.
1. The voltage change should be first step if switch from LD or SWFFC
to ND with no_od_mode. And it should be last step if switch from
OD (no_od_mode is false)
2. The NIC clock rate must be higher MEDIA AXI clock, otherwise writing to
registers in Mediamix will cause system hang due to HW issue on axi2apb.
So must increase NIC clock prior than MEDIA AXI when switch from LD or
SWFFC to ND. And decrease NIC clock at last when switch from OD to ND.Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
15 Oct, 2024
1 commit
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If set the mode to the same mode as current mode, return
directly.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
12 Oct, 2024
1 commit
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According the latest RM, the LD frequency of NIC should be 250M
for i.MX91.Signed-off-by: Pengfei Li
Reviewed-by: Ye Li
27 Aug, 2024
1 commit
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ele_voltage_change_req() should only be called when switching
between OD and LD/SWFFC. Fix this issue by using the no_od_mode
property, otherwise i.MX91 will call this API when switching to
LD/SWFFC.Signed-off-by: Pengfei Li
Reviewed-by: Ye Li
Acked-by: Jason Liu
23 Jul, 2024
1 commit
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According to iMX91 ADD, some AXI bus clock rates are different with
iMX93 at ND and LD as below. Fix this issue by setting a separate
operating_mode for each platform.iMX91:
ND LD
wakeup_axi_clk_root 250Mhz 200Mhz
nic_clk_root 333Mhz 200Mhz
media_axi_clk_root 200Mhz 200MhziMX93:
ND LD
wakeup_axi_clk_root 333Mhz 200Mhz
nic_clk_root 400Mhz 250Mhz
media_axi_clk_root 333Mhz 200MhzSigned-off-by: Pengfei Li
Reviewed-by: Ye Li
19 Jul, 2024
2 commits
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Because imx93_lpm needs to call ELE API, so adding the IMX_SEC_ENCLAVE
dependency to avoid build issue.Signed-off-by: Ye Li
Reviewed-by: Dong Aisheng -
Call ELE voltage change start and finish APIs when set VDD_SOC
to OD or LD.Signed-off-by: Ye Li
Reviewed-by: Pankaj Gupta
Reviewed-by: Jacky Bai
23 Apr, 2024
1 commit
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The rpmsg message should only be used when rpmsg life cycle device is
supported by remote processors, otherwise there will be kernel panic:
[ 41.256628] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
[ 41.301441] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 41.308503] pc : rpmsg_lifecycle_suspend_noirq+0x60/0xe4
[ 41.313919] lr : dpm_run_callback.constprop.0+0x74/0x134
[ 41.395118] Call trace:
[ 41.397654] rpmsg_lifecycle_suspend_noirq+0x60/0xe4
[ 41.402738] dpm_run_callback.constprop.0+0x74/0x134
[ 41.407790] __device_suspend_noirq+0xa8/0x1b8
[ 41.412321] dpm_noirq_suspend_devices+0x178/0x204
[ 41.417216] dpm_suspend_noirq+0x24/0x98Reviewed-by: Jacky Bai
Signed-off-by: Peng Fan
07 Apr, 2024
1 commit
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When changing to OD mode, the NIC_AXI frequency should be
updated firstly before other clocks.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
22 Nov, 2023
1 commit
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* pm/next: (53 commits)
LF-10339-1 Revert "soc: imx: imx8m-blk-ctrl: set LCDIF panic read hurry level"
LF-9095: gpc: fwnode: Make imx pgc power domain also set the fwnode
LF-8359 soc: imx: imx93-blk-ctrl: fix power up domain fail during early noriq resume
LF-8093 pmdomain: imx: imx8mp-blk-ctrl: add missing HSIO noc setting
LF-9380-1: soc: imx8mp_blk: Add fdcc clock to hdmimix domain
...
15 Nov, 2023
1 commit
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For i.MX9 family, the ANAMIX SoC ID register may not be
accessible from linux side on all the platforms. using
SiP call to get the soc info is more feasible way to
handle chip difference.Signed-off-by: Jacky Bai
Reviewed-by: Peng Fan
30 Oct, 2023
28 commits
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Change iMX8ULP A35 CPU frequency to default 800Mhz for OD, 650Mhz for ND.
And can support some special parts with higher CPU frequency in OD.Change NIC_AD to 452Mhz for OD, 328Mhz for ND
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
Reviewed-by: Jacky Bai -
On i.MX8ULP, the ddr controller can NOT support the automatic
refresh rate adjustment based on the MR4 contents. Instead, the
DDR controller used on i.MX8ULP can generate interrupt if LP4 MR4
reports temperature change(MR4.TUF=1). User can adjust the refresh
rate in the irq handler when LP4 reports temperature change.There is no other good place to hold the ISR based refresh rate
adjustment support, just put it into the imx8ulp lpm file.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li -
There's a potential A-B/B-A deadlock between Clock and PM domain
framework in current kernel. Accessing PD clocks in genpd->power_on()/
power_off() callback is unsafe as mentioned in the commit
2b31e22d5376 ("PM: domains: add pm domain clocks support").This patch switches to use the in core GENPD_FLAG_PM_PD_CLK feature for
imx8mp only to avoid such possible deadlock issue.Signed-off-by: Dong Aisheng
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Add a simple userspace controlled interface to adjust
the DDR frequency based on the user needs to save power.
It can also be customized to add more control to adjust
clock like bus fabric or other peripherals.if sys_dvfs_enabled is true, system level OD/ND mode can be switched,
otherwise, only do ddr frequency scaling just as beforeusage:
1. put DDR into low frequency:
echo 1 > /sys/devices/platform/imx8ulp-lpm/enable2. DDR exit from low frequency:
echo 0 > /sys/devices/platform/imx8ulp-lpm/enableSigned-off-by: Jacky Bai
Reviewed-by: Ye Li -
On i.MX8ULP, when APD side enters suspend, need to notify RTD side
to do lifecycle management, so add suspend/resume support for this
purpose.We need to add virtual platform device to implement the suspend/resume
callback as the rpmsg device driver don't have the support for device
specific suspend/resume support.Signed-off-by: Jacky Bai
Acked-by: Peng Fan
Reviewed-by: Ye Li -
Add rpmsg life cycle support on i.MX8ULP for APD side low power mode
state coordination with M core by sending rpmsg to M4 core. Currently,
only need to send nofity to M core for reboot/poweroff case. APD side
need to send rpmsg to M core side to let it know that APD side will
enter 'DPD' HW mode or do reboot. For both cases, M core side need to
re-init the rpmsg service when APD out of reset.Signed-off-by: Jacky Bai
Reviewed-by: Robin Gong -
Allow i.MX8M power domain driver to be loaded as module.
And set the default value of IMX8M_PM_DOMAINS as ARCH_MXC.Signed-off-by: Jindong Yue
Reviewed-by: Jacky Bai -
Symbol driver_deferred_probe_check_state is not exported
in kernel, blocking this pm driver built as module.
Using -EPROBE_DEFER to replace it.Signed-off-by: Jindong Yue
Reviewed-by: Jacky Bai -
Some power domain need to be runtime always on to keep
the peripherals's weekup ability, for such power domain,
add the 'GENPD_FLAG_RPM_ALWAYS_ON' flag.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang -
Add the active wakeup flag if a power domain has such requirement.
Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
(cherry picked from commit c545e706e40d8ae663b70fd248c7f1565dca45da) -
The i.MX8M family is a set of NXP product focus on delivering
the latest and greatest video and audio experience combining
state-of-the-art media-specific features with high-performance
processing while optimized for lowest power consumption.i.MX8MQ, i.MX8MM, i.MX8MN, even the furture i.MX8MP are all
belong to this family. A GPC module is used to manage all the
PU power domain on/off. But the situation is that the number of
power domains & the power up sequence has significate difference
on those SoCs. Even on the same SoC. The power up sequence still
has big difference. It makes us hard to reuse the GPCv2 driver to
cover the whole i.MX8M family. Each time a new SoC is supported in
the mainline kernel, we need to modify the GPCv2 driver to support
it. We need to add or modify hundred lines of code in worst case.
It is a bad practice for the driver maintainability.This driver add a more generic power domain driver that the actual
power on/off is done by TF-A code. the abstraction give us the
possibility that using one driver to cover the whole i.MX8M family
in kernel side.Signed-off-by: Jacky Bai
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i.MX91/P only support ND/LD mode, so do necessary changes to
support it.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li -
Current idle strap value 256 seems too small to meet most of the
ddr access perforamce requirement like ML benchmark & high resolution
video playback, so enlarge the default idle count time to 32768 to
meet the high perforamnce case ddr latency requirement.For power consumption, when the system is idle, set idle strap to
'32768' only introduces very small VDD_SOC power increase. It should
be acceptable considering basic function & performance impact.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li -
Fix a typo to correct the nic frequency setting in LD mode
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li -
i.MX8MP UID is actually 128bits, the higher 64bits is at 0xE00.
Signed-off-by: Peng Fan
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The value of Device ID for i.MX91P is the same as i.MX93, so use
compatible to distinguish them.Signed-off-by: Alice Guo
Reviewed-by: Ye Li -
When the value of OSCCA_FUSE_READ_DIS is 1, i.MX93 is not allowed to
access the OCOTP registers. So split i.MX93 SoC device support
from soc-imx8m.c. The first 4 words of bank 6, a total of 128 bits, are
OTP_UNIQ_ID of i.MX93.Signed-off-by: Alice Guo
Reviewed-by: Ye Li -
Use '%u' to print the idle strap value to let user more
easier to interpret and understand it.Signed-off-by: Jacky Bai
Reviewed-by: Peng Fan -
When user want to get the current system drive mode, show
the current ddr frequency info too. So refine the code for
this purpose.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li -
Update the mode switching flow to fix some corner case issue:
1) when system switching from LD mode ND mode, the voltage should
be increased before increase the clock frequency;
2) when switching to LD/SWFFC mode, NIC AXI clock should be reduded
after all the clocks have been slow down to fix a random hang issue.
more likely, the NIC AXI can only be slow down when A55 related clock
has been reduced.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li -
Refine the system wide run mode flow to add the dynamic
ld mode switching support. usage example:
OD mode:
echo 0 > /sys/devices/platform/imx93-lpm/mode;ND mode:
echo 1 > /sys/devices/platform/imx93-lpm/mode;LD mode:
echo 2 > /sys/devices/platform/imx93-lpm/mode;LD mode with DDR scaling by SWFFC:
echo 3 > /sys/devices/platform/imx93-lpm/mode;when DDR highest frequency is 3733MTS & system is running at
OD mode, the auto clock gating will be enabled by default to
balance the power & performance. For other case, need to be
enabled by user explictly based on actual case.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
Acked-by: Peng Fan -
Based on i.MX93 CCB#44, the ND mode voltage should be
updated from 0.8V to 0.85V.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
Acked-by: Jason Liu -
Add the DDR and SoC run mode(OD/OD) dynamic power saving support
on i.MX93. This low power control module provides four interface
to control the system wide OD/ND mode swithcing with DDR frequency
scaling by HWFFC, DDR scaling down to a frequency < half of the full
speed, DDR auto clock gating enable & auto clock gating idl strap
to fine tuning the performance & power based on the user case.the supported controls are exported through the sys interface:
sys/devices/platform/imx93-lpm/mode;
sys/devices/platform/imx93-lpm/swffc;
sys/devices/platform/imx93-lpm/auto_clk_gating;
sys/devices/platform/imx93-lpm/idle_delay;a). 'mode' is used to switching the od/nd mode with DDR HWFFC;
b). 'swffc' is used for scaling the DDR frequency to a lower one
with system switched to ND mode;c). 'auto_clk_gating' is used to enable the DDR auto clock gating.
d). 'idle_delay' is used for fine tuning the DDR auto clock gating
strap. a larger value means after the DDRC AXI idle for that
clock count, the DDRC will put the DRAM into self-refresh with
clock gated to save power.example:
1. switch the system to ND mode:
echo nd > sys/devices/platform/imx93-lpm/mode;Signed-off-by: Jacky Bai
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Adding i.MX93 SoC device register function providers revision,
serial_number and soc_id for other drivers to use.NOTE: soc-imx9.c depends on imx-ocotp-fsb-s400.c, so add
"depends on NVMEM_IMX_OCOTP_FSB_S400" otherwise we may meet the issue
imx9_init_soc: probe of 47510000.efuse:imx93-soc failed with error -2"
which appears at a low probability because nvmem_add_cells_from_of()
sometimes has not registered nvmem cells when soc-imx9.c calls
nvmem_cell_read_u64().Reviewed-by: Ye Li
Reviewed-by: Peng Fan
Signed-off-by: Alice Guo -
Modify config as tristate and add module license to support
building imx8m soc driver as module.Signed-off-by: Jindong Yue
Reviewed-by: Jacky Bai -
Add rpmsg life cycle support on i.MX8ULP for APD side low power mode
state coordination with M core by sending rpmsg to M4 core. Currently,
only need to send nofity to M core for reboot/poweroff case. APD side
need to send rpmsg to M core side to let it know that APD side will
enter 'DPD' HW mode or do reboot. For both cases, M core side need to
re-init the rpmsg service when APD out of reset.Signed-off-by: Jacky Bai
Reviewed-by: Robin Gong -
Fix below section mismatch build warning:
WARNING: modpost: vmlinux.o(.text+0x6b20b8): Section mismatch in reference
from the function imx8_soc_info() to the function .init.text:imx8mq_noc_init()
The function imx8_soc_info() references
the function __init imx8mq_noc_init().
This is often because imx8_soc_info lacks a __init
annotation or the annotation of imx8mq_noc_init is wrong.Signed-off-by: Jacky Bai
Reviewed-by: Peng Fan -
The config for lcdif should be removed, and need to add vpu
qos setting by default. this patch is just to add back the
vpu qos config that is missed when resolving cherry-pick
conflict for patch:
3a3f54750294: MLK-19380 driver: soc: update the noc QoS setting on imx8mqSigned-off-by: Jacky Bai
Reviewed-by: Anson Huang
