02 Aug, 2023
2 commits
08 May, 2023
1 commit
03 May, 2023
1 commit
15 Nov, 2022
1 commit
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As the eDMA can NOT work well on i.MX93 A0 silicon, lpuart/lpspi use
CPU mode for data transfer. when the cpuidle is enabled, the IRQ
response latency will increase, then lead to lpuart/lpspi test failure
in high baudrate mode.Enlarge the cpuidle latency setting to let cpu has less changce to enter
low powe mode state to mitigate the latency impacted for lpuart/lpspi
high baudrate mode as much as possible.this is just a workaround to partially improve the case, it can works
well most of the time. it is not a solid fix. if still meet issue in real
case on A0 silicon, user should use cpu_dma_latency setting or disable cpuidle
as needed.Signed-off-by: Jacky Bai
Reviewed-by: Peng Fan
Acked-by: Jason Liu
10 Nov, 2022
1 commit
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Without this patch, the initial video_pll1 rate is 594MHz, so the pixel
clock rate of RM67199 MIPI DSI panel would derive from it and get 118.8MHz.
With that pixel clock rate, it turns out the panel fails to show weston
GUI at the first time weston GUI starts though the Linux boot logo penguins
can be shown correctly. Based on experiments, the issue can be avoided
if the panel driver does not call mipi_dsi_dcs_get_display_brightness()
in ->get_brightness() callback at the Linux boot logo penguin stage. If
the system finishes a full reboot cycle, the issue doesn't happen since
the backlight brightness won't be gotten at that boot logo stage. The
root cause of the issue is unclear. To workaround this issue, align the
pixel clock rate with the same panel's pixel clock rate on i.MX8mp EVK,
which is 115.5MHz and derived from 1.0395GHz video PLL. RM67191 MIPI DSI
panel display and ADV7535 DSI to HDMI display are ok after applying this
patch. The only impact is the refresh rate of the MIPI DSI panels would
be a little bit lower, but it aligns with i.MX8mp EVK.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying
Acked-by: Jason Liu
07 Nov, 2022
3 commits
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Up until now, the external MDIO controller frequency values relied
either on the default ones out of reset or on those setup by u-boot.
Let's just properly specify the MDC frequency in the DTS so that even
without u-boot's intervention Linux can drive the MDIO bus.Fixes: 0420dde30a90 ("arm64: dts: ls208xa: add the external MDIO nodes")
Signed-off-by: Ioana Ciornei -
Up until now, the external MDIO controller frequency values relied
either on the default ones out of reset or on those setup by u-boot.
Let's just properly specify the MDC frequency in the DTS so that even
without u-boot's intervention Linux can drive the MDIO bus.Fixes: bbe75af7b092 ("arm64: dts: ls1088a: add external MDIO device nodes")
Signed-off-by: Ioana Ciornei -
Up until now, the external MDIO controller frequency values relied
either on the default ones out of reset or on those setup by u-boot.
Let's just properly specify the MDC frequency in the DTS so that even
without u-boot's intervention Linux can drive the MDIO bus.Fixes: 6e1b8fae892d ("arm64: dts: lx2160a: add emdio1 node")
Fixes: 5705b9dcda57 ("arm64: dts: lx2160a: add emdio2 node")
Signed-off-by: Ioana Ciornei
26 Oct, 2022
2 commits
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Enable support for XDP (supported on DPAA1, DPAA2, ENETC) and for AF_XDP
(supported on DPAA2, ENETC).Signed-off-by: Vladimir Oltean
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This reverts commit 349b847ce2a19b655daa9e4585a33fa9f9e2dd39.
The issue of LF-7367 was introduced by the commit . Now
the commit is reverted, so revert this patch too.Signed-off-by: Wei Fang
Reviewed-by: Jun Li
25 Oct, 2022
4 commits
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NXP vendor tree is using a private busfreq [1] driver to do ddr and
bus fabric scalling rather than using upstream ddrc & interconnect
driver which is still immature. And actually there's no i.MX driver users
of ICC in current vendor kernel. So removing them in order to avoid
confusing to customers.Some other vendor dtbs using those nodes are also disabled to avoid
build break.1. drivers/soc/imx/busfreq-imx8mq.c
Reviewed-by: Jacky Bai
Reviewed-by: Peng Fan
Signed-off-by: Dong Aisheng -
NXP vendor tree is using a private busfreq [1] driver to do ddr and
bus fabric scalling rather than using upstream ddrc & interconnect
driver which is still immature. And actually there's no i.MX driver users
of ICC in current vendor kernel. So removing them in order to avoid
confusing to customers.Some other vendor dtbs using those nodes are also disabled to avoid
build break.1. drivers/soc/imx/busfreq-imx8mq.c
Reviewed-by: Jacky Bai
Reviewed-by: Peng Fan
Signed-off-by: Dong Aisheng -
NXP vendor tree is using a private busfreq [1] driver to do ddr and
bus fabric scalling rather than using upstream ddrc & interconnect
driver which is still immature. And actually there's no i.MX driver users
of ICC in current vendor kernel. So removing them in order to avoid
confusing to customers.Some other vendor dtbs using those nodes are also disabled to avoid
build break.1. drivers/soc/imx/busfreq-imx8mq.c
Reviewed-by: Jacky Bai
Reviewed-by: Peng Fan
Signed-off-by: Dong Aisheng -
NXP vendor tree is using a private busfreq [1] driver to do ddr and
bus fabric scalling rather than using upstream ddrc & interconnect
driver which is still immature. And actually there's no i.MX driver users
of ICC in current vendor kernel. So removing them in order to avoid
confusing to customers.Some other vendor dtbs using those nodes are also disabled to avoid
build break.1. drivers/soc/imx/busfreq-imx8mq.c
Reviewed-by: Jacky Bai
Reviewed-by: Peng Fan
Signed-off-by: Dong Aisheng
21 Oct, 2022
3 commits
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GPIO.17 and GPIO.22 form pcal6524 IO expander should be set to low
voltage. Otherwise SAI and MICFIL can't work properly.Reviewed-by: Shengjiu Wang
Signed-off-by: Chancel Liu -
DPDK is not capable to handle any type of congestion
or back-pressure. So if there is congestion on the network,
HW can generate PAUSE frames to limit the traffic and packets
can be dropped in the DPDK.So in this patch, removing the pause property from switch and
ethernet ports.Signed-off-by: Gagandeep Singh
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The ptn5110 is sharing interrupt line with gpio expander. The interrupt
line should be gpio3_26 rather gpio3_27 on imx93-9x9-qsb.Signed-off-by: Xu Yang
Reviewed-by: Li Jun
20 Oct, 2022
1 commit
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Add qca,rx-clk-enable property to keep rx clock output when SoC suspend.
Signed-off-by: Clark Wang
Reviewed-by: Wei Fang
19 Oct, 2022
3 commits
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This reverts commit a9cf2a9c902655753c9e621078503d97c3d8bb32.
Although this option looks harmless it looks it breaks RM67199 panel.
So revert the patch until we figure out what's going on.Reviewed-by: Dong Aisheng
Signed-off-by: Daniel Baluta -
This reverts commit 2f2a46c5d65973e6557881c9f8f1a5ea74fd84c6.
Enabling CONFIG_DYNAMIC_DEBUG raised some concerns about performance
regression. So disable this until we have some numbers to compare.Reviewed-by: Dong Aisheng
Signed-off-by: Daniel Baluta -
Enable DMA for lpi2c on imx8dxl platforms
Signed-off-by: Han Xu
Reviewed-by: Clark Wang
18 Oct, 2022
1 commit
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Low drive mode requires pdm clock frequency lower than 133MHz,
So reduce it to achieve the target, the 49MHz can be used
for ND/OD/LD.Signed-off-by: Shengjiu Wang
Reviewed-by: Chancel Liu
17 Oct, 2022
2 commits
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This allows users to enable/disable debug level messages at runtime
make thus easier to debug kernel code.This increases the kernel image size by 2%.
Reviewed-by: Aisheng Dong
Signed-off-by: Daniel Baluta -
We need first to select CONFIG_EXPERT=y and then we can enable some
of SOF debugging features. This does not increase kernel Image size!Debugging with SOF is done via /sys/kernel/debug/sof interface.
Reviewed-by: Paul Olaru
Signed-off-by: Daniel Baluta
14 Oct, 2022
1 commit
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Currently, hsio_root clock rate is 24MHz which is not on its optimal
status. Change it to 133MHz.Before:
osc_24m 9 9 0 24000000 0 0 50000 Y
hsio_root 2 2 0 24000000 0 0 50000 Y
usb_controller 1 1 0 24000000 0 0 50000 YAfter:
sys_pll_pfd1 1 1 0 800000000 0 0 50000 Y
sys_pll_pfd1_div2 8 9 0 400000000 0 0 50000 Y
hsio_root 1 1 0 133333334 0 0 50000 Y
usb_controller 0 0 0 133333334 0 0 50000 NSigned-off-by: Xu Yang
Reviewed-by: Li Jun
13 Oct, 2022
1 commit
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Need to support IW612 on imx8mn evk board through the micro-sd slot.
- insert IW612 2EL module + muRata M.2-to-usd adapter into micro-SD slot
- no BT supportNote: Since IW612 wifi chip needs more delay than other wifi chips to
complete the host interface initialization after power up, otherwise the
internal state of IW612 may be unstable, resulting in the failure of the
SDIO3.0 switch voltage, so need to add 20ms regulator startup delay for
IW612.Signed-off-by: Sherry Sun
Reviewed-by: Haibo Chen
12 Oct, 2022
7 commits
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Adding the display nodes and GPU nodes for the lpddr4 validation board in
the default configuration. The DisplayPort devicetree, *-dp.dtb, will have
LVDS1 and MIPI DSI 1 also enabled. This change aligns with the imx8qm-mek.dts
and older Linux releases before the 5.X kernel.Signed-off-by: Oliver F. Brown
Reviewed-by: Laurentiu Palcu -
Enable epxp for iMX93-9x9-qsb board
Signed-off-by: Guoniu.zhou
Reviewed-by: Robby Cai -
Build in MT9M114 driver by default
Signed-off-by: Guoniu.zhou
Reviewed-by: Robby Cai -
Add MT9M114 camera device nodes for iMX93-9x9 board
Signed-off-by: Guoniu.zhou
Reviewed-by: Robby Cai -
Add MT9M114 device node for iMX93-11x11 EVK board.
AP1302 and adp5585_isp are located in an external daughter card which
will not be used in MT9M114 camera case, so disable them.In iMX93-11x11-EVK board, SAI3 and CAN2 share the same pins with RPi
interface by using IO MUX, so disable SAI3 and CAN2 in RPi caseSigned-off-by: Guoniu.zhou
Reviewed-by: Robby Cai -
Add parallel csi device node for iMX93 platform
Signed-off-by: Guoniu.zhou
Reviewed-by: Robby Cai -
The following two properties of RTL PHY have been obsoleted in the
latest realtek phy driver.
rtl821x,aldps-disable;
rtl821x,clkout-disable;
And replaced by the new properties as below:
realtek,aldps-enable;
realtek,clkout-disable;
Since the ADLPS mode of RTL PHY defaults to be disabled, so there
is unnecessary to add such a property in the dts node.
Addtionally, RTL8211F(D)(I)-VD-CG does not support to disable clkout.
Therefore, it's safe to remove the obsolete properties and no need
to add new properties.Signed-off-by: Wei Fang
Reviewed-by: Li Jun
11 Oct, 2022
2 commits
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This patch creates a sound card with 2 links:
* esai0 -> cs42888
* sai1 -> wm8960With this we can use both codecs found on imx8qxp/imx8qm and implement
more complex scenarios like AEC.Signed-off-by: Daniel Baluta
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Add cpuidle support on i.MX93.
Signed-off-by: Jacky Bai
Reviewed-by: Peng Fan
10 Oct, 2022
4 commits
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The SCMI PD for HIFI4 DSP is missed. DSP can work after boot, because
SPL has enabled its PS and SRAM by default, and ATF enables HIFI4 PS
with DSI PS and keeps SRAM during APD suspend/resume. But once RTD is
suspend/resume, HIFI4's SRAM power is disabled, and no one will enable
it, this causes issue to use DSP afterward.Signed-off-by: Ye Li
Reviewed-by: Jacky Bai -
There are two issues in current USDHC clocks setting:
1. The PLL3 PFD2 maximum frequency is 332Mhz, we can't set it to 389Mhz
as USDHC clock parent. Because PLL3 PFD0 is used for NIC, PFD1 is used
for audio, the only choice is PFD3 which can reach to 400Mhz.2. USDHC1 and USDHC2 maximum PCC clock rate is 200Mhz in OD, and 100Mhz in
ND/LD, when PTE or PTF is used.The patch adjusts clock parent to PLL3 PFD3 DIV1 for USDHC0, PLL3
PFD3 DIV2 for USDHC1 and USDHC2. And set the max rate to meet restrictions.Signed-off-by: Ye Li
Reviewed-by: Haibo Chen -
The audio power enable pin for wm8962 sound card is GPIO16 of pcal6524
IO expander.Reviewed-by: Shengjiu Wang
Signed-off-by: Chancel Liu -
Enabe wm8962 sound card on imx93-9x9 quick start board. The SAI used
by this card works on synchronous mode. Both the transmitter and
receiver use the receiver bit clock and frame sync in this mode.Reviewed-by: Shengjiu Wang
Signed-off-by: Chancel Liu
