08 Jun, 2017
40 commits
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When resuming from VLLS mode, the wdog will be reset, the first we configure
the wdog, an initial timeout value should be write into the TOVAL register,
otherwise, the wdog will not be initialized successfully.Signed-off-by: Bai Ping
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Add i.MX7ULP 14x14 arm2 board support.
Signed-off-by: Anson Huang
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There are 2 usdhc instances on i.MX7ULP, previous
usdhc1 should be usdhc0, now add the correct usdhc1 node.Signed-off-by: Anson Huang
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Add gpio port control clocks, and add them to init table.
If the gpio clock is controlled by gpio driver, the watchdog
reset will occur due to unknown reason, we need to debug it
if we need driver to control its clocks.Signed-off-by: Peter Chen
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On i.MX7ULP, the IOMUXC PAD register has IBE and OBE bit to control
the input/output buffer if a PIN wants to use as GPIO function.Additonally, on i.MX7ULP, the MUX reg and CONFIG reg is shared in one
register and the GPIO function select in the MUX is not index zero as
on I.MX6 SOC, add support in code for i.MX7ULP GPIO function.Signed-off-by: Bai Ping
Signed-off-by: Fugang Duan
Signed-off-by: Peter Chen -
Add GPIO (PCTLC,D,E,F) support
Signed-off-by: Fugang Duan
Signed-off-by: Peter Chen -
Add direction set for mx7ulp.
Signed-off-by: Fugang Duan
Signed-off-by: Peter Chen -
In commit: b1a04e6ed63,(MLK-13413), the tempmon node is
wrongly disabled. so fix it in this patch.Signed-off-by: Bai Ping
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Enable wdog driver in defconfig.
Signed-off-by: Bai Ping
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When the wdog driver is added for i.MX7ULP, it is no need to
do wdog driver disable when resume from VLLS mode as wdog driver
will handle it.Signed-off-by: Bai Ping
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Add watchdog driver for i.MX7ULP.
Signed-off-by: Bai Ping
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Add 'timeout-sec' property for wdog node of i.MX7ULP.
Signed-off-by: Bai Ping
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Improve the fractional divider calculation accuracy use
continued fraction method.Signed-off-by: Bai Ping
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RBB needs to be enabled for VLPS mode to save
power, it can save ~0.4mA on VDD_DIG1.Signed-off-by: Anson Huang
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Add RTC node for i.MX7ULP, re-use SNVS RTC.
Signed-off-by: Anson Huang
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On i.MX7ULP, there are options to select SPLL or SPLL PFD
as SPLL output clock SPLL_SEL, so the SPLL option for
sys_sel mux should be from SPLL_SEL, NOT from SPLL directly.Previous:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 2 2 531648000 0
sys_sel 1 1 531648000 0
core_div 2 2 531648000 0
plat_div 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 1 1 503666526 0
spll_pfd_sel 0 0 503666526 0
spll_sel 0 0 503666526 0
After fixed:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 2 2 503666526 0
spll_pfd_sel 1 1 503666526 0
spll_sel 1 1 503666526 0
sys_sel 1 1 503666526 0
core_div 1 1 503666526 0
plat_div 1 1 503666526 0CORE_DIV clock will be enabled automatically when PLAT_DIV
is enabled, so we can skip it in clks_init_on.Now that sys_sel clock tree is correct, no need to have SPLL_PFD0
in clks_init_on, as it will be enabled automatically because of
PLAT_DIV.Signed-off-by: Anson Huang
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Per design request, all PLLs/PFDs need to be disabled before
entering low power mode, here for VLPS/VLLS mode, add this
procedure.For VLPS mode, DDR is also in self-refresh mode, so NVCC_DRAM_SW
can be turned off as well, add this support.Signed-off-by: Anson Huang
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change parent clock to pll3_pfd2 and calculate out a desired pixel clock
rate. This patch fixed the following warning.
"imx_epdc_v2_fb 20f4000.epdc: Unable to get an accurate EPDC pix clkdesired = 40000000, actual = 63529412"Signed-off-by: Robby Cai
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Add eMMC support (8 bit mode) for ulp-evk board.
Signed-off-by: Haibo Chen
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When enter VLLS mode, DRAM is in self-refresh, NVCC_DRAM_SW
can be off to save power.As the static io-map formula is no longer feasible on i.MX7ULP,
here we change it to ioremap for creating iram tlb.Remove the physical module base address in pm_info structure
to save iram space.Signed-off-by: Anson Huang
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Add PTC1 pin as GPIO on i.MX7ULP SOM board, it is
to control NVCC_DRAM_SW during suspend/resume.Signed-off-by: Anson Huang
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Support i.MX6SLL OTP.
There are 4 works in bank7/bank8.
When read, use address offset.
When prog, use bank/index, note that bank7/bank8 we treat
them a single bank when prog.Tested GP41 and GP31 read/write on eng sample chip.
Signed-off-by: Peng Fan
(cherry picked from commit f8698b66fcbec7409b738a4c5b05ba87f0342cf8) -
The previous code only support i.MX6UL EVK RevA, RevB, RevC PHY KSZ8081
with fixed silicon revision.
Different silicon revision may have different phy fixup init setting.i.MX6UL EVK RevC1 apdate new silicon revision PHY. After debug and tune,
the revision still need the same phyfix setting.So, add Ethernet PHY KSZ8081 new silicon revision fixup setting.
Signed-off-by: Fugang Duan
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Fix typo of iomux wifi function.
Signed-off-by: Fugang Duan
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As TPM default clock parent is changed to OSC which is 24MHz,
to keep its frequency as 3MHz, need to update its divider
from 16 to 8.Signed-off-by: Anson Huang
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As FIRC may be NOT accurate enough and it also can
be disabled when M4 goes into VLPR mode, so using
OSC as TMP clock parent is better.Signed-off-by: Anson Huang
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The PCC clock bit field definition is as below:
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5So previous clock driver sets PCC clock parent to
start from index value 1 by setting CLK_MUX_INDEX_ONE
flag, however it has an issue of getting clock parent
when the register field value is 0, below is the clk
get parent code from clk driver:if (val && (mux->flags & CLK_MUX_INDEX_BIT))
val = ffs(val) - 1;if (val && (mux->flags & CLK_MUX_INDEX_ONE))
val--;The val is 0, so the parent will be returned as first
clock parent in PCC register field which is 001b,
that will cause setting clk parent fail when the
reset value is 0 and we try to set clk parent to
option 1, as clk driver thinks current clk parent
is same as the new parent.Fix this issue by adding dummy clock as option0, ths
clk gate is controlled by bit 30, so it would NOT impact
gating function.Signed-off-by: Anson Huang
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add IPG clock for gpc to delay 2us for PU power up.
Signed-off-by: Robin Gong
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(sw + sw2iso) delay after raise power up request to pgc is still not
enough stable, so we have to delay 2us to make sure pgc power up
successfully as v3.14. Align the power off flow with v3.14 too.Signed-off-by: Robin Gong
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Correct a macro definition in mxsfb.c
In framebuffer driver, a macro define LCDIF_CTRL2n register bits[23-21] value
is 0x3, but according to reference manual, it should be 0x4, so correct it.Signed-off-by: Guoniu.Zhou
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Fix typo in compatible string.
Signed-off-by: Bai Ping
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Add charger driver in dts.
Signed-off-by: Robin Gong
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Add usdhc2 support for imx6sll-lpdr3-arm2 board.
Signed-off-by: Haibo Chen
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For imx6sll-evk board, if eMMC connected, all the pad of
eMMC should be fixed to 1.8v. Otherwise the current leakage
will pull up the VCCQ to 2.6v, which will impatch usdhc1
and usdhc3 SD3.0 voltage switch.This patch set the LVE of pad SD2_RST and SD2_STROBE, and
config the vqmmc to fixed 1.8v, make sure the driver set
pad I/O voltage of usdhc2 fixed to 1.8v, not impact the
VCCQ which support usdhc1 and usdhc3 SD3.0 1.8v voltage.And accord to IC suggestion, clock and strobe pad need to
config as pull-down. So change all the clock/strobe pad's
PUS to 0.eMMC data4/5 has branch on evk board, which make the data
signal quality very bad, need to cut off these branch of
data4/5, this hardware rework is hard to do on all the evk
board. So currently HS400 do not enable, just support eMMC
HS200 mode.Signed-off-by: Haibo Chen
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On i.MX6SLL EVK and ARM2 board, the pins for I2C3 should be set
to 1.8V voltage(set the LVE bit to 1) to decrease the current
leakage from these pins.Signed-off-by: Bai Ping
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When resume from VLPS mode on i.MX7ULP, APLL is NOT
valid yet, but MMDC clock is from APLL, so need to
wait for it valid before operating MMDC.Signed-off-by: Anson Huang
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Add i.MX7ULP cpuidle support, 3 levels idle as below:
1. patial stop mode 3;
2. patial stop mode 2;
3. patial stop mode 1.PSTOP1 - Partial Stop with system and bus clock disabled
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
PSTOP3 - Partial Stop with system clock enabled and bus clock enabledAll drivers has DMA function need to add pm_qos
API to prevent cpuidle from entering PSTOP 1/2.Signed-off-by: Anson Huang
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On some SoCs such as i.MX7ULP, there is no busfreq
driver, but cpuidle has some levels which may disable
system/bus clocks, so need to add pm_qos to prevent
cpuidle from entering low level idles and make sure
system/bus clocks are enabled when usdhc is active.Signed-off-by: Anson Huang
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arch/arm/boot/dts/vfxxx.dtsi:256.20-28 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:293: recipe for target
'arch/arm/boot/dts/vf500-colibri-eval-v3.dtb' failed
make[2]: *** [arch/arm/boot/dts/vf500-colibri-eval-v3.dtb] Error 1
arch/arm/Makefile:327: recipe for target 'dtbs' failed
make[1]: *** [dtbs] Error 2Signed-off-by: Peter Chen
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On i.MX7ULP, IOMUX's mux and pad config are in
same register, but mux field is different, add
support in pinctrl driver.Signed-off-by: Anson Huang