08 Jun, 2017
40 commits
-
On i,MX6SL, no NUM and DENUM register, so this PLL should not
be registered as IMX_PLLV3_GENERIC type PLL, it should be
registered as IMX_PLLV3_SYSV2.Signed-off-by: Bai Ping
-
Added clock enable and disable to the probe and remove functions
where appropriate.Signed-off-by: Dan Douglass
-
According the the latest datasheet, we updated the lowest
OPP to 198MHz. So we need to update the cpufreq code to fix
the syttem hang issue when run 'cpufreq-info' in low bus mode
on i.MX6ULL.Signed-off-by: Bai Ping
-
According to the latest datasheet(Rev. 0,09/2016), update the
setpoints of i.MX6ULL. we add 25mV margin to cover IR drop
and board tolerance.LDO enable:
Freq VDD_SOC VDD_ARM
528MHz 1.175V 1.175V
396MHz 1.175V 1.025V
198MHz 1.175V 0.95VLDO bypass
Freq VDD_SOC VDD_ARM
528MHz 1.175V 1.175V
396Mhz 1.175V 1.175V
198MHz 1.175V 1.175VSigned-off-by: Bai Ping
-
cs42xx8 is a 24 bit device, the maximum supported bit is 24bit.
So remove the S32_LE from the supported list.Signed-off-by: Shengjiu Wang
-
Enable DCP in imx6ull.dtsi
Signed-off-by: Dan Douglass
-
Enable DCP driver in imx_v7_defconfig
Signed-off-by: Dan Douglass
-
Enable DCP support for imx6 series.
Signed-off-by: Dan Douglass
-
Enable hardware RNG in imx6ull.dtsi
Signed-off-by: Dan Douglass
-
Enable the RNG driver in imx_v7_defconfig
Signed-off-by: Dan Douglass
-
Signed-off-by: Dong Aisheng
-
Add DTS file imx6ull-9x9-evk.dts which is originated from i.MX6UL EVK with
some changes:
1. Include imx6ull.dtsi as base
2. sim2 is removed.
3. Move GPIO5 pins setting to iomuxc-snvs
4. Enable CSI and ov5640Signed-off-by: Ye Li
-
running following vte stress test will meet "mx6s-csi 21c4000.csi: mx6s_csi_irq_handler Rx fifo overflow"
and cannot be stopped to capture again.i=0; while [ $i -lt 3000 ];do v4l2_capture_emma -D /dev/video1 -C 2 -M 0 -J 30,4 -W 640 -H 480;i=`expr $i + 1`;done
This patch adds the same handling as BIT_HRESP_ERR_INT for BIT_RFF_OR_INT
(RxFiFo OverFlow) to reset CSI as a recovery.Signed-off-by: Robby Cai
-
As i.MX6's PLL2 also support a fractional-N
synthesizer, so we need to consider the NUM
and DENOM's value to get a correct rate, as
fraction may be used in some cases.Remove round_rate and set_rate for PLL2, as
it is NOT allowed to be changed in kernel
dynamically, otherwise, PFDs and DDR may NOT
work normally, it normally should be changed
in u-boot before DDR is enabled.Signed-off-by: Anson Huang
-
For imx6ull-14x14-evk emmc rework board, usdhc2 HS200 I/O timing is
not stable @176MHz, for write operation, crc error shows up. So this
patch change the frequence to 132MHz.Signed-off-by: Haibo Chen
-
Enable eMMC for i.MX6UL EVK rework board due to the pad conflict with NAND
and Micro-SD.Signed-off-by: Haibo Chen
-
Enable eMMC for i.MX6ULL EVK rework board due to the pad conflict with NAND
and Micro-SD.Signed-off-by: Haibo Chen
-
Add lcdif alias name.
Signed-off-by: Sandor Yu
-
Add fb name check function pwm_backlight_check_fb_name(),
pwm driver can banding to fb with fb name when driver working
in device tree architecture.Signed-off-by: Sandor Yu
-
Fix hdmicec pinctrl setting error.
Signed-off-by: Sandor Yu
-
i.MX6SX LDB will connect to LCDIF2.
And LCDIF2 pixel clock can not re-parent when it's on.
So default setting clock parent to ldb_di0.Signed-off-by: Sandor Yu
-
Add dts for imx6ull 14x14 evk board's USB certification test
Signed-off-by: Peter Chen
-
On i.MX6ULL, when the system entering the low bus mode, system will enter
low power run mode in which the cpufreq is at 24MHz. If we run
'cpufreq-info' until, the cpu frequency will be change from 24MHz to 99MHz,
this will lead to system enter low power idle wrong, and system will hang
in low power idle.Add the ARM core clock handling code to fix this issue.
Signed-off-by: Bai Ping
-
Enable NAND for i.MX6ULL EVK board which need to be reworked due to the
pin conflict with QSPI and SD2.Signed-off-by: Han Xu
-
Add Murata Type ZP (BCM4339) module support on i.MX6ULL platforms:
- i.MX6ULL EVK (SD1 slot) + Murata adapter V2.0Signed-off-by: Fugang Duan
-
enable csi and ov564x
Signed-off-by: Robby Cai
-
The PIN is conflicted with CSI camera. Need to disable CSI to make lcdif work.
Signed-off-by: Robby Cai
-
Add DTS file imx6ull-14x14-evk.dts which is originated from i.MX6UL EVK with
some changes:
1. sim2 is removed.
2. Move GPIO5 pins setting to iomuxc-snvsSigned-off-by: ye li
-
Add the sanity check for drect's width and height in
pxp_set_scaling() to avoid div0 exception.Signed-off-by: Fancy Fang
-
The dynamicly allocated 'pseudo_palette' area should be
freed when unused to avoid memory leak.Signed-off-by: Fancy Fang
-
Refine the 'fb_info' field in 'mxsfb_info' that change this
field to be a pointer which can reduce the 'mxsfb_info' size.
Besides, store the 'host' data to fb_info->par to replace the
unnecessary 'to_imxfb_host' macro.Signed-off-by: Fancy Fang
-
The function 'platform_set_drvdata' will be called twice
during the probing stage. And the second calling is not
good and not necessary.Signed-off-by: Fancy Fang
-
QSPI only support upto 16 LUT slots while the QSPI commands are more
than this number, reserve the last two slots for dynamic change (most
commands used in pairs). Later all extra supported commands will be add
in dynamic lut table.Signed-off-by: Han Xu
-
Missing the 'break' will cause the function return failure
when the 'bits_per_pixel' is 32 which should be supported.Signed-off-by: Fancy Fang
-
The default bpp should be set to a proper value if it is
not set yet during mipi panel display initialization.Signed-off-by: Fancy Fang
-
Using a dedicated kernel thread to dispatch all the client
requests which can support asynchronous multi-task.Signed-off-by: Fancy Fang
-
The test case is one p2p playback + two m2m converter running
simultaneously. There are three root cause for this issue:1. hw_free() of p2p may be called twice in the end, which cause
release twice of one pair, if another pair request is called between
this two release, there will be issue.2. In m2m close(), the asrc_priv->pair[i] will be set NULL twice,
which is same issue as 1.3. when output rate is more than eight multiple of input rate for m2m,
the last_period_size should be larger.Signed-off-by: Shengjiu Wang
-
Correct the imx7d pcie legacy interrupters.
INTA 157
INTB 156
INTC 155
INTD 154Signed-off-by: Richard Zhu
-
Change the hardware reset gpio to 'GPIO6_IO15' for mipi dsi to
allow fec2 and mipi dsi can run at the same time. This needs
some hardware rework as follows:
"
1. Replace R631 with 100K resistor;
2. Remove D14, D24;
3. Solder the Cathode of the diode to R471,
you can use BAT54HT1(ONSEMI) or NSR0320MW2T1G(ONSEMI);
4. Solder the wire to the Anode end of the diode;
5. Scrape the solder mask(Green oil) of the MIPI Reset via,
then solder the end of the wire to the via.
"Signed-off-by: Fancy Fang
-
The 32 bpp pixel format which is passed to pxp should be
'PXP_PIX_FMT_RGB32' instead of 'PXP_PIX_FMT_RGB24', since
only 'PXP_PIX_FMT_RGB32' can be recognized by lcdif.Signed-off-by: Fancy Fang