20 Apr, 2018
4 commits
-
This node will be used by the OCRAM driver in optee to:
* Get the OCRAM start address for power management in optee.
* Add an entry that will overwrite ocrams nodes and dynamically reduce
the OCRAM available for mmio-sram in Linux.That way we do not touch the legacy Linux boot and remove the dedicated
optee device tree.Signed-off-by: Clement Faure
Reviewed-by: Peng Fan
(cherry picked from commit e96a3bcd754dee0aef3519bc08979985493be52c) -
This change affects all i.MX 6 with PL310 L2 Cache controller.
When Linux runs in Non-secure World the PL310 has already
been initialized by the ARM secure World running OP-TEE os.
However, in order to have a proper Linux Initialization all the
L2 cache ways have been locked by the secure world.This patch unlock all the ways during pl310 initialization.
Signed-off-by: Cedric Neveux
(cherry picked from commit be7971b62e0c77cf70f828868a5d5a4184a926d2) -
7ULP uses the same mmdc profiling block as i.mx6q. Added the
"fsl,imx6q-mmdc" compatible string to enable the mmdc profiling
feature.Signed-off-by: Shenwei Wang
-
Linus reported hitting the bandwidth warning, but it is indeed
pretty useless - improve it by printing the rate configuration
and make it only warn once, for both warnings here.Reported-by: Linus Torvalds
Signed-off-by: Johannes Berg
19 Apr, 2018
1 commit
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Incorrect condition check causes -ETIME return only
happen when next event is equal to current counter, and
it would cause various system issue like RCU stalls etc.,
the correct case should be whenever next event is less
than current counter, -ETIME should be returned. Correct
the type cast during return condition check to make it
work right.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
18 Apr, 2018
2 commits
-
Signed-off-by: Franck LENORMAND
(cherry picked from commit 0b122f882429a82274fc99439b5d73986b731672) -
Fix the following warnings in CAAM SM:
drivers/crypto/caam/sm_store.c: In function 'blacken_key_jobdesc':
drivers/crypto/caam/sm_store.c:141:19: warning: cast from pointer
to integer of different size [-Wpointer-to-int-cast]
tmpdesc[idx++] = (u32)key;
^
drivers/crypto/caam/sm_store.c:153:19: warning: cast from pointer
to integer of different size [-Wpointer-to-int-cast]
tmpdesc[idx++] = (u32)key;
^
drivers/crypto/caam/sm_store.c: In function 'blob_encap_jobdesc':
drivers/crypto/caam/sm_store.c:274:19: warning: cast from pointer
to integer of different size [-Wpointer-to-int-cast]
tmpdesc[idx++] = (u32)secretbuf;
^
drivers/crypto/caam/sm_store.c: In function 'blob_decap_jobdesc':
drivers/crypto/caam/sm_store.c:390:19: warning: cast from pointer
to integer of different size [-Wpointer-to-int-cast]
tmpdesc[idx++] = (u32)outbuf;
^
drivers/crypto/caam/sm_store.c: In function 'slot_get_base':
drivers/crypto/caam/sm_store.c:569:9: warning: cast from pointer
to integer of different size [-Wpointer-to-int-cast]
return (u32)(ksdata->base_address);
^
drivers/crypto/caam/sm_store.c: In function 'sm_keystore_slot_load':
drivers/crypto/caam/sm_store.c:789:6:
warning: unused variable 'i' [-Wunused-variable]
u32 i;Signed-off-by: Franck LENORMAND
(cherry picked from commit b6bd87e624bbe30b9be19c3f8ccb8f5526e4186b)
17 Apr, 2018
2 commits
-
On the i.MX7ULP EVK Rev.B baord, the backlight brigntness driver circuit
is updated. A RC filter is added on the MP3301's EN pin. So the PWM's frequency
should be change to 20KHZ. for EN pin, A DC voltage from 0.7V to 1.4V can control
the LED current from 0% to 100%. the backlight brightness level also need to be
updated.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit 82555e15a5f958c09492d0103425dc30bc7cd927) -
In i.MX7ULP TPM PWM module, it has a pre-scale divider,
this divider setting is missed, so fix it.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit 3ffd915e44320a8142698ca3f6e19c30ec434f61)
13 Apr, 2018
3 commits
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The default display interface on i.MX7ULP EVK board is the HDMI
interface, and a hardware rework is required to support the MIPI
panel. To match the current board design, added the HDMI node in
the imx7ulp-evk.dts and created a new file named imx7ulp-evk-mipi.dts.Signed-off-by: Shenwei Wang
Reviewed-by: Andy Duan -
commit a56e6e190015 ("MLK-17961 dts: imx7ulp-evk: add non-removable
property for wifi sdio") add non-removable property, sd1 slot on
base board share the same usdhc with wifi, and the sd1 slot support
card detect, so for sd1 slot, need to remove the non-removable
property.Signed-off-by: Haibo Chen
Reviewed-by: Andy Duan
(cherry picked from commit 2a40d8123aff4b4fb7a5cbf286d0c308a42c2fc7) -
This patch fix resume failure in freeze suspend mode on i.mx7ULP
("echo freeze > /sys/power/state") while pressing onoff key or
enabling rtc alarm wakeup. In freeze mode, kernel can only be woken
up by drivers which register wakup source such as 'device_init_wakeup'
or 'irq_set_irq_wake', otherwise, kernel will wait for irq handler
freeze_wake(). Unfortunately, our NMI interrupt which used to wakeup
A7 by M4 is not a common device and request irq as 'IRQF_NO_SUSPEND'
which means feeze_wake() never get chance to run while wakeup by any
event from M4 such as RTC, ONOFF. In this case, use pm_system_wakeup()
instead in NMI interrupt handle to trigger freeze_wake() directly.Signed-off-by: Robin Gong
Reviewed-by: Anson Huang
12 Apr, 2018
28 commits
-
The microphone only connect to left input, when record stereo channel
data, the right channel is mute. Add 'ADC Data Output Select' mixer
control that user can select the wanted configure. The default setting
is 'Left Data = Left ADC; Right Data = Left ADC'.Signed-off-by: Shengjiu Wang
(cherry picked from commit cce63c3e843b7d705df6e36adffc0226bfe40e42) -
The logic of 'if' check for the mult is wrong, this will lead
to set rate to PLL type failed. Additionally, remove the
unnecessary 'CLK_IS_CRITICAL' flags.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit a67aa226b9d0d294b51cfc43371fe78a005dfae4) -
The gpu3d/2d clock rate for 7ulp B0 board is 400M, increase it
Signed-off-by: yuchou gan
(cherry picked from commit b51ae7e98ccfd9e25697d3e5b9795699917496ea) -
the original patch will skip CMA memory allocation with CMA_LIMIT flag,
that enforces GPU memory allocation from virtual pool with MMU mapping,
then both 2D and 3D performance will have performance regression on i.MX6.Revert "6.2.4.p1-0044-CL142820-check-flag-match-even-try-to-allocate-from-"
This reverts commit 8a8cbf389ad56dc49685ea078698087be867655a.
Signed-off-by: Xianzhong
(cherry picked from commit 951e42c0ec05d4cdaf739eadd5fd40c2b8321b10) -
Add poweron key support on i.mx7ulp-evk board since M4 take
over snvs on B0 chip.Signed-off-by: Robin Gong
Reviewed-by: Anson Huang -
Add non-removable property for usdhc1 that is used as Murata
1PJ wifi sdio interface, which means wifi card always is present.Signed-off-by: Shenwei Wang
Signed-off-by: Fugang Duan
Tested-by: Fugang Duan -
If GPIO is connected to an IRQ then it should not request it as
GPIO function only when free its IRQ resouce.Tested-by: Haibo Chen
Signed-off-by: Fugang Duan
Signed-off-by: Anson Huang
Signed-off-by: Robin Gong <yibin.gong@nxp.com -
We've got some fixups for DPR IP in the new i.MX8QXP silicon.
To address the cropping issue(TKT344978), the new IP changes the
FRAME_2P_PIX_X/Y_CTRL(@F0h and @100h) register definitions to be
FRAME_PIX_X/Y_ULC_CTRL. Thus, we should not set the two registers
for the new IP. FRAME_PIX_X/Y_ULC_CTRL will be programmed after
we figure out how to use them to do fb x/y offset for tile formats.Signed-off-by: Liu Ying
-
We don't have correct support for fb x/y source offset for tile formats.
The buffer address calculation is wrong when the offset is non-zero.
Also, finer offset needs a fix in silicon(TKT344978). So, let's do not
support the offset currently. We may add it back after we figure out
how the updated silicon supports the offset.Signed-off-by: Liu Ying
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commit 3a0a397ff5ff upstream.
Now that we've standardised on SMCCC v1.1 to perform the branch
prediction invalidation, let's drop the previous band-aid.
If vendors haven't updated their firmware to do SMCCC 1.1, they
haven't updated PSCI either, so we don't loose anything.Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
no falkor/thunderx2/vulcan in arch/arm64/kernel/cpu_errata.c -
commit b092201e0020 upstream.
Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
It is lovely. Really.Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
no qcom hyp functions in
arch/arm64/kernel/bpi.S
arch/arm64/kernel/cpu_errata.c -
commit f2d3b2e8759a upstream.
One of the major improvement of SMCCC v1.1 is that it only clobbers
the first 4 registers, both on 32 and 64bit. This means that it
becomes very easy to provide an inline version of the SMC call
primitive, and avoid performing a function call to stash the
registers that would otherwise be clobbered by SMCCC v1.0.Reviewed-by: Robin Murphy
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex Shi -
commit ded4c39e93f3 upstream.
Function identifiers are a 32bit, unsigned quantity. But we never
tell so to the compiler, resulting in the following:4ac: b26187e0 mov x0, #0xffffffff80000001
We thus rely on the firmware narrowing it for us, which is not
always a reasonable expectation.Cc: stable@vger.kernel.org
Reported-by: Ard Biesheuvel
Acked-by: Ard Biesheuvel
Reviewed-by: Robin Murphy
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex Shi -
commit e78eef554a91 upstream.
Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed,
let's do that at boot time, and expose the version of the calling
convention as part of the psci_ops structure.Acked-by: Lorenzo Pieralisi
Reviewed-by: Robin Murphy
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex Shi -
commit 09a8d6d48499 upstream.
In order to call into the firmware to apply workarounds, it is
useful to find out whether we're using HVC or SMC. Let's expose
this through the psci_ops.Acked-by: Lorenzo Pieralisi
Reviewed-by: Robin Murphy
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex Shi -
commit f72af90c3783 upstream.
We want SMCCC_ARCH_WORKAROUND_1 to be fast. As fast as possible.
So let's intercept it as early as we can by testing for the
function call number as soon as we've identified a HVC call
coming from the guest.Tested-by: Ard Biesheuvel
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex Shi -
commit 6167ec5c9145 upstream.
A new feature of SMCCC 1.1 is that it offers firmware-based CPU
workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides
BP hardening for CVE-2017-5715.If the host has some mitigation for this issue, report that
we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the
host workaround on every guest exit.Tested-by: Ard Biesheuvel
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
no sve support in arch/arm64/include/asm/kvm_host.h
mv changes from virt/kvm/arm/psci.c to arch/arm/kvm/psci.c
using cpus_have_cap instead of cpus_have_const_cap -
commit a4097b351118 upstream.
We're about to need kvm_psci_version in HYP too. So let's turn it
into a static inline, and pass the kvm structure as a second
parameter (so that HYP can do a kern_hyp_va on it).Tested-by: Ard Biesheuvel
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
mv changes from virt/kvm/arm/psci.c to arch/arm/kvm/psci.c -
commit 90348689d500 upstream.
For those CPUs that require PSCI to perform a BP invalidation,
going all the way to the PSCI code for not much is a waste of
precious cycles. Let's terminate that call as early as possible.Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Catalin Marinas
Signed-off-by: Alex Shi -
commit 09e6be12effd upstream.
The new SMC Calling Convention (v1.1) allows for a reduced overhead
when calling into the firmware, and provides a new feature discovery
mechanism.Make it visible to KVM guests.
Tested-by: Ard Biesheuvel
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
mv change from virt/kvm/arm/psci.c to arch/arm/kvm/psci.c -
commit 58e0b2239a4d upstream.
PSCI 1.0 can be trivially implemented by providing the FEATURES
call on top of PSCI 0.2 and returning 1.0 as the PSCI version.We happily ignore everything else, as they are either optional or
are clarifications that do not require any additional change.PSCI 1.0 is now the default until we decide to add a userspace
selection API.Reviewed-by: Christoffer Dall
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
mv chagnes from virt/kvm/arm/psci.c to arch/arm/kvm/psci.c -
commit 84684fecd7ea upstream.
Instead of open coding the accesses to the various registers,
let's add explicit SMCCC accessors.Reviewed-by: Christoffer Dall
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
mv change from virt/kvm/arm/psci.c to arch/arm/kvm/psci.c -
commit d0a144f12a7c upstream.
As we're about to trigger a PSCI version explosion, it doesn't
hurt to introduce a PSCI_VERSION helper that is going to be
used everywhere.Reviewed-by: Christoffer Dall
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
mv change form virt/kvm/arm/psci.c to arch/arm/kvm/psci.c -
commit 1a2fb94e6a77 upstream.
As we're about to update the PSCI support, and because I'm lazy,
let's move the PSCI include file to include/kvm so that both
ARM architectures can find it.Acked-by: Christoffer Dall
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex ShiConflicts:
need kvm/arm_psci.h in files:
arch/arm64/kvm/handle_exit.c
arch/arm/kvm/psci.c and arch/arm/kvm/arm.c
no virt/kvm/arm/arm.c and virt/kvm/arm/psci.c -
commit f5115e8869e1 upstream.
When handling an SMC trap, the "preferred return address" is set
to that of the SMC, and not the next PC (which is a departure from
the behaviour of an SMC that isn't trapped).Increment PC in the handler, as the guest is otherwise forever
stuck...Cc: stable@vger.kernel.org
Fixes: acfb3b883f6d ("arm64: KVM: Fix SMCCC handling of unimplemented SMC/HVC calls")
Reviewed-by: Christoffer Dall
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Alex Shi -
commit aa6acde65e03 upstream.
Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing
and can theoretically be attacked by malicious code.This patch implements a PSCI-based mitigation for these CPUs when available.
The call into firmware will invalidate the branch predictor state, preventing
any malicious entries from affecting other victim contexts.Co-developed-by: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Catalin Marinas
Signed-off-by: Alex ShiConflicts:
no falkor in arch/arm64/kernel/cpu_errata.c -
commit 30d88c0e3ace upstream.
It is possible to take an IRQ from EL0 following a branch to a kernel
address in such a way that the IRQ is prioritised over the instruction
abort. Whilst an attacker would need to get the stars to align here,
it might be sufficient with enough calibration so perform BP hardening
in the rare case that we see a kernel address in the ELR when handling
an IRQ from EL0.Reported-by: Dan Hettena
Reviewed-by: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Catalin Marinas
Signed-off-by: Alex Shi -
commit 5dfc6ed27710 upstream.
Software-step and PC alignment fault exceptions have higher priority than
instruction abort exceptions, so apply the BP hardening hooks there too
if the user PC appears to reside in kernel space.Reported-by: Dan Hettena
Reviewed-by: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Catalin Marinas
Signed-off-by: Alex ShiConflicts:
expand enable_da_f to 'msr daifclr, #(8 | 4 | 1)'
in arch/arm64/kernel/entry.S
