20 Feb, 2019
3 commits
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Set IR built-in on imx8 boards.
Signed-off-by: Joakim Zhang
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Enable IR on imx8mq-evk board.
Signed-off-by: Joakim Zhang
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Enable IR on imx8mm-evk board.
Signed-off-by: Joakim Zhang
19 Feb, 2019
2 commits
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The following commit:
459a5fac54d - MLK-20263: drm/imx/dcss: fix channel-0 line shift
removed the 5 tap filter for vertical luma/chroma when YUV formats were
used.Problem is that when the 7 tap filter is used for vertical luma/chroma,
artifacts can be seen on screen when scaling.RGB can, however, function correctly with only 7 tap filter.
This patch partially reverts the above patch and also does some cosmetic
changes when calling the dcss_scaler_filter_design() using false/true
instead of 0/1 for use_5_taps argument.Signed-off-by: Laurentiu Palcu
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i.MX8QXP has separated irq, and shared irq for lpuart with eDMA,
it is better for uart to use separated irq although there has
no function impact.Reviewed-by: Robin Gong
Signed-off-by: Fugang Duan
18 Feb, 2019
1 commit
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Unlock hw_lock before calling v4l2_m2m_job_finish to avoid deadlock:
v4l2_m2m_job_finish -> v4l2_m2m_try_schedule -> job_ready locks hw_lock
v4l2_m2m_job_finish -> v4l2_m2m_try_run -> device_run locks hw_lockSigned-off-by: Mirela Rabulea
Reviewed-by: Laurentiu Palcu
15 Feb, 2019
5 commits
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Add the speeding grading fuse check to limit the highest speed
of cpu. fuse bits value define as below:
speed_grading bits[1:0] freq(MHz)
0x0 800
0x1 1000
0x2 1300
0x3 1500Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
(cherry picked from commit 0b42acc89cc8752c4a952c116c7905106208e92d) -
Update SCFW APIs to SCFW commit:
004247e14afc ("SCF-341 Fix bug in setting large slice clock divider")Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
Reviewed-by: Peng Fan
(cherry picked from commit 89add27a115c3b378d7151299b2919c14a1427ef) -
Update resource ID table to SCFW commit:
004247e14afc ("SCF-341 Fix bug in setting large slice clock divider")Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
Reviewed-by: Peng Fan
(cherry picked from commit 8fa8f318eeac939604e2616fd7a6e1fd10d837a0) -
Galcore kernel panic when reading from sysfs during modprobe,
This issue occurs when gc sysfs entries are read while the modprobe
of the galcore module is in progress.Register the GC debugfs attributes in sysfs after the driver data-structures
have been initialized, instead of before.Add defensive sanity checks in all _show() functions used by debugfs
attributes, to check for NULL pointers before dereferencing them.
Return -ENXIO in case of NULL pointers.Signed-off-by: Xianzhong
(cherry picked from commit 3283efbeadbc11cb38146cb7874becfecf27f981) -
GPU hang will happen when run multiple test instances.
link command could be used for context switch often,
it is not reliable to check wait or link command only.need check command address first, then check command.
Signed-off-by: Xianzhong
(cherry picked from commit a7d6f50164039334f371fef1575de7d80d10aa58)
14 Feb, 2019
6 commits
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LSIO_GPIO1 drive the IOEXP_RST signal, its power is off in system
suspend to save power, which introduces reset pulse for expander IO.To avoid unexpected reset, set the PIN to "latch" status before the
GPIO controller is power off during suspend.Signed-off-by: Fugang Duan
(cherry picked from commit: 0c859a75a465d39d10784d95895188bb6f02492e) -
VUY444 is supported by PXP HW but driver miss it. so add it
Signed-off-by: Guoniu.Zhou
(cherry picked from commit 57e9b876954170cd0718eb8af8666573ebb26bb4) -
For the number of requested source buffer, driver need one at least.
For the number of requested destination buffer, driver need three at least.Signed-off-by: Guoniu.Zhou
(cherry picked from commit c3d33d6ad971b2e03c034e14696d64549245f918) -
Fix potential dead lock issue
Signed-off-by: Guoniu.Zhou
(cherry picked from commit 322beb5215ea921dd30c0974cd17465de306927b) -
Refer to ISI validataion code, there is no need to enable ISI
mem2mem read done interrupt and driver can handle buffers in
frame received interrupt serviceRemove 50ms delay when enable ISI AXI read, it will improve
performance obviouslySigned-off-by: Guoniu.Zhou
(cherry picked from commit bdabe035cd5c57d713f824e61f120213ed9357ba) -
Checking parameters from userspace befor applying for different format
Signed-off-by: Guoniu.Zhou
(cherry picked from commit 47ff54238f138be015756a45afb0af58b52e5a02)
13 Feb, 2019
2 commits
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If pointer is released, but it didn't set to NULL, it will be a wild
pointer. It may cause unexpected error, and hard to debug.
To avoid this bug, define a macro to release pointer and set it to NULL.Signed-off-by: ming_qian
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MXC_VPU_MALONE -> MXC_VPU_LEGACY
vpu-malone -> vpu_legacyMXC_VPU_DECODER -> MXC_VPU_MALONE
vpu-decoder-b0 -> vpu_maloneSigned-off-by: ming_qian
12 Feb, 2019
21 commits
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Adding support for HDCP 1.4 and 2.2 based upon upstream 4.19 kernel
use of "Content Protection" connector property.Signed-off-by: Oliver Brown
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Cleaning up HDCP code to remove coding errors and warnings in calling
functions. Also, removed printk's from HDCP APIs.Signed-off-by: Oliver Brown
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Added function to read HDCP disable fuse.
Signed-off-by: Oliver Brown
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This patch adds HDCP register definitions for HDMI and DP HDCP
adaptations.HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
where as HDCP2.2 register offsets in DPCD offsets are defined at
drm_dp_helper.h.v2:
bit_field definitions are replaced by macros. [Tomas and Jani]
v3:
No Changes.
v4:
Comments style and typos are fixed [Uma]
v5:
Fix for macros.
v6:
Adds _MS to the timeouts to represent units [Sean Paul]
v7:
Macro DP_HDCP_2_2_REG_EKH_KM_OFFSET renamed [Uma]
Redundant macro is removed [Uma]Signed-off-by: Ramalingam C
Reviewed-by: Sean Paul
Acked-by: Sean Paul (for merging through drm-intel)
Signed-off-by: Daniel Vetter
Link: https://patchwork.freedesktop.org/patch/msgid/1540806351-7137-6-git-send-email-ramalingam.c@intel.com -
This patch defines the hdcp2.2 protocol messages for authentication.
v2:
bit_fields are removed. Instead bitmasking used. [Tomas and Jani]
prefix HDCP_2_2_ is added to the macros. [Tomas]
v3:
No Changes.
v4:
Style and spellings are fixed [Uma]
v5:
Fix for macros.
v6:
comment for Type is improved [Sean Paul]
v7:
%s/HDCP_2_2_LPRIME_HALF_LEN/HDCP_2_2_V_PRIME_HALF_LEN [Uma]
%s/uintxx_t/uxx
v8:
%s/eceiver_id/receiver_idSigned-off-by: Ramalingam C
Reviewed-by: Uma Shankar
Acked-by: Sean Paul
Signed-off-by: Daniel Vetter
Link: https://patchwork.freedesktop.org/patch/msgid/1540806351-7137-5-git-send-email-ramalingam.c@intel.com -
In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)So macro for bitmasking the device_count is fixed(0x3F->0x7F).
v3:
Retained the Rb-ed.
v4:
%s/drm\/i915/drm [rodrigo]
v5:
Added "Fixes:" and HDCP keyword in subject [Rodrigo, Sean Paul]Signed-off-by: Ramalingam C
Fixes: 495eb7f877ab drm: Add some HDCP related #defines
cc: Sean Paul
Reviewed-by: Sean Paul
Signed-off-by: Sean Paul
Link: https://patchwork.freedesktop.org/patch/msgid/1522929802-22850-1-git-send-email-ramalingam.c@intel.com -
HDCP compliant Repeaters can support max of 127 devices and max
depth of 7 for downstream topology.If these max limits are exceeded, repeater will set the
topology error flags MAX_CASCADE_EXCEEDED and/or MAX_DEVS_EXCEEDED
in Bstatus followed by asserting READY/CP_IRQ for HDCP transmitter.This patch check for these error flags as soon as READY bit is asserted.
Signed-off-by: Ramalingam C
[seanpaul fixed checkpatch alignment issue]
Signed-off-by: Sean Paul
Link: https://patchwork.freedesktop.org/patch/msgid/1516254488-4971-5-git-send-email-ramalingam.c@intel.com -
Added content_type property to drm_connector_state
in order to properly handle external HDMI TV content-type setting.v2:
* Moved helper function which attaches content type property
to the drm core, as was suggested.
Removed redundant connector state initialization.v3:
* Removed caps in drm_content_type_enum_list.
After some discussion it turned out that HDMI Spec 1.4
was wrongly assuming that IT Content(itc) bit doesn't affect
Content type states, however itc bit needs to be manupulated
as well. In order to not expose additional property for itc,
for sake of simplicity it was decided to bind those together
in same "content type" property.v4:
* Added it_content checking in intel_digital_connector_atomic_check.
Fixed documentation for new content type enum.v5:
* Moved patch revision's description to commit messages.v6:
* Minor naming fix for the content type enumeration string.v7:
* Fix parameter name for documentation and parameter alignment
in order not to get warning. Added Content Type description to
new HDMI connector properties section.v8:
* Thrown away unneeded numbers from HDMI content-type property
description. Switch to strings desription instead of plain
definitions.v9:
* Moved away hdmi specific content-type enum from
drm_connector_state. Content type property should probably not
be bound to any specific connector interface in
drm_connector_state.
Same probably should be done to hdmi_picture_aspect_ration enum
which is also contained in drm_connector_state. Added special
helper function to get derive hdmi specific relevant infoframe
fields.v10:
* Added usage description to HDMI properties kernel doc.v11:
* Created centralized function for filling HDMI AVI infoframe, based
on correspondent DRM property value.Acked-by: Hans Verkuil
Acked-by: Daniel Vetter
Signed-off-by: Stanislav Lisovskiy
Link: https://patchwork.freedesktop.org/patch/msgid/20180515135928.31092-2-stanislav.lisovskiy@intel.com
[vsyrjala: clean up checkpatch multiple blank lines warnings]
Signed-off-by: Ville Syrjälä -
In preparation for implementing HDCP in i915, add some HDCP related
register offsets and defines. The dpcd register offsets will go in
drm_dp_helper.h whereas the ddc offsets along with generic HDCP stuff
will get stuffed in drm_hdcp.h, which is new.Changes in v2:
- drm_hdcp.h gets MIT license (Daniel)
Changes in v3:
- None
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- SPDX licenseCc: Daniel Vetter
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link: https://patchwork.freedesktop.org/patch/msgid/20180108195545.218615-5-seanpaul@chromium.org -
This patch adds a new optional connector property to allow userspace to enable
protection over the content it is displaying. This will typically be implemented
by the driver using HDCP.The property is a tri-state with the following values:
- OFF: Self explanatory, no content protection
- DESIRED: Userspace requests that the driver enable protection
- ENABLED: Once the driver has authenticated the link, it sets this valueThe driver is responsible for downgrading ENABLED to DESIRED if the link becomes
unprotected. The driver should also maintain the desiredness of protection
across hotplug/dpms/suspend.If this looks familiar, I posted [1] this 3 years ago. We have been using this
in ChromeOS across exynos, mediatek, and rockchip over that time.Changes in v2:
- Pimp kerneldoc for content_protection_property (Daniel)
- Drop sysfs attribute
Changes in v3:
- None
Changes in v4:
- Changed kerneldoc to recommend userspace polling (Daniel)
- Changed kerneldoc to briefly describe how to attach the property (Daniel)
Changes in v5:
- checkpatch whitespace noise
- Change DRM_MODE_CONTENT_PROTECTION_OFF to DRM_MODE_CONTENT_PROTECTION_UNDESIRED
Changes in v6:
- NoneReviewed-by: Daniel Vetter
Signed-off-by: Sean Paul[1] https://lists.freedesktop.org/archives/dri-devel/2014-December/073336.html
Link: https://patchwork.freedesktop.org/patch/msgid/20180108195545.218615-4-seanpaul@chromium.org -
Currently, the phy_ref clock is also used by dsi_bridge nodes (nwl-dsi
driver) in order to set the phy_ref rate needed by a specific mode.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Currently, the phy_ref clock is also used by dsi_bridge nodes (nwl-dsi
driver) in order to set the phy_ref rate needed by a specific mode.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Reconfigure the LCDIF, DCSS and DSI clocks such that we can use
mode_valid to determine which mode can be supported or not by a specific
display pipe (DCSS+DSI or LCDIF+DSI).Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Implement the mode_valid in dcss-crtc to filter-out unsupported modes.
In dcss-crtc, just use the mode_valid and mode_fixup functions from
dcss-dtg.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Implement mode_valid and mode_fixup functions for the dcss-crtc
driver so that DCSS can filter-out unsupported modes and save the
configuration for the supported ones.
Use mode_fixup to apply the saved configuration of a supported mode.
The mechanism to determine if a mode is supported or not is made in
dcss-dtg.Also, add 2 new clocks:
- pll: this is the video PLL that provides the pixel clock; it's rate
needs to be set such that the pixel clock can be achieved
- pll_src*: this is an oscillator that can be used as source clock for
the video pll; currently, there are possible maximum 3 pll sources,
defined as pll_src1, pll_src2 and pll_src3. The actual clocks that
can be used as pll source are: CLK_25M, CLK_27M and CLK_PHY_27MHZRemoved the pdiv_clk and pout_clk and replaced them with pix_clk,
since out of those two only one was used: pdiv_clk, representing the pixel
clock.In dcss-dtg, each mode is tested and if we can achieve it's pixel
clock we save this mode configuration into an internal list and apply this
configuration later on when mode_fixup is called.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Implement mode_valid and check functions from
drm_simple_display_pipe_funcs such that we can filter-out modes that
cannot be driven by this controller.
Add 3 new clocks:
- video_pll: this is the PLL that provides the pixel clock; it's rate
needs to be set such that the pixel clock can be achieved
- osc_25: this is an oscillater that can be used as source clock for the
video_pll; default freq is 25MHz
- osc_27: same as above, but with freq of 27MHzDepending on the display mode used, the video_pll needs to have it's
clock source a 25MHz or 27MHz oscillator. Also, the video_pll rate needs
to be set to a rate that can be evenly divided to obtain the required
pixel clock. All these settings (clock source and video_pll rate) are
saved in mode_valid, then applied before mode needs to be set in the
check function.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
The PL111 needs to filter valid modes based on memory bandwidth.
I guess it is a pretty simple operation, so we can still claim
the DRM KMS helper pipeline is simple after adding this (optional)
vtable callback.Reviewed-by: Eric Anholt
Reviewed-by: Daniel Vetter
Signed-off-by: Linus Walleij
Link: https://patchwork.freedesktop.org/patch/msgid/20180220072859.3386-1-linus.walleij@linaro.org -
Some pixel clocks are not working with DSI. Until a better solution is
found, just filter-out the display modes by their clocks.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Panels can request a higher clock than the one that can actually be
driven by the CRTC, in order to have more time for DSI commands.
If this is the case, make sure that the crtc_clock used is one that can
actually be driven for current chosen phy_ref rate.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
This patch removes the exported function nwl_dsi_get_bit_clock that was
used by nwl_dsi-imx driver in order to configure the phy driver speed
and move this configuration directly into the nwl-dsi driver.
This function is now used directly by nwl-dsi to verify which mode can or
cannot be supported by the DSI PHY.
Also, in nwl-dsi, add support for mode_valid and add each supported mode
into a list kept internally so that it can apply the needed
configuration (phyref rate, dsi lanes, bit-clock) later when the mode is
used.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Remove the variables 'format', 'vc' and 'dsi_mode_flags' since we can
use the directly from the dsi_device object.
Also, fix the VACTIVE value (currently, -1 is subtracted from it but it
wasn't necessary).Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu
