23 Feb, 2017
40 commits
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cherry-pick below patch:
ENGR00275004-1 input: touchscreen: max11801_ts: Add DCM mode for max11801 ADC
We need add DCM mode/AUX mode for ADC converter function of max11801, so that
it can be used to read voltage of battery. Meanwhile, let the driver based on
device tree. The patchset is based on below patch (V3.5.7):commit 4001774cf51f0140ae7e4e8e0ec1d86475790682
Author: Rong Dian
Date: Fri Jan 18 14:24:28 2013 +0800Engr00240284-1 MAX11801: Add DCM aux adc sample function
1.Add direct conversion mode operations
2.Add aux adc sample functionSigned-off-by: Robin Gong
(cherry picked from commit 57b11d40431336c28f15a8a67af41907948c42b6)
(cherry picked from commit 0cf609eb332e206fa6dac3df25ae906c7ab8bd4c) -
Need increase the FORCE_MAX_ZONEORDER to 14 for high resolution camera
(GPU 2D user case). The default value 11(4MB) is not enough now.Signed-off-by: Jason Liu
(cherry picked from commit fff642ffe868cb55f5caec0501e36fd28b6ece50) -
Add dts support for pxp v4l2 output on imx6sx sabreauto
board.Signed-off-by: Fancy Fang
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Add dts support for pxp module on the imx6sx sabreauto
board.Signed-off-by: Fancy Fang
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Add dts support for pxp v4l2 output on imx6sx sdb
board.Signed-off-by: Fancy Fang
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Add dts support for pxp module on the imx6sx sdb
board.Signed-off-by: Fancy Fang
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Add dts support for ldb module on the imx6sx
sabreauto board.Signed-off-by: Fancy Fang
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Add dts support for backlight and pwm4 modules on
imx6sx sabreauto board.Signed-off-by: Fancy Fang
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Update the i.MX6SX operating points to comply with the latest
datasheet. Latest i.MX6SX datasheet of Rev.F, 1/2015 adds the
198MHz setpoint. For the RevB board, the VDD_ARM and ADD_SOC
are connected together, so the voltage for 198MHz needs to be
set to 1.175V. for the general setting, add a 25mV margin to
cover the board IR drop.Signed-off-by: Bai Ping
(cherry picked from commit 62bd7207e6346f404589ed8305971c9815d2cf8b) -
Add pinctrl restore to support LPSR.
Signed-off-by: Robin Gong
(cherry picked from commit f7d40aa30ca2fe337ba9bb8f7eaca4393db900be) -
add gpio keys.
Signed-off-by: Robin Gong
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add gpio keys, please attach main board to test this function, since those
gpio pins are located on main board.Signed-off-by: Robin Gong
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Add lcdif dts support on imx6sl evk board.
Signed-off-by: Fancy Fang
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Add pxp v4l2 output support for imx6sl evk board.
Signed-off-by: Fancy Fang
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Add hdcp dtb file for imx6q/dl sabresd board.
Signed-off-by: Sandor Yu
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Initial the mxc mipi dsi driver.
Baseline copied from imx_3.14.y branch.Signed-off-by: Sandor Yu
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Add dcic driver property to imx6q/dl sabresd/auto
and imx6sx sdb board.Signed-off-by: Sandor Yu
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Initial the mxc dcic driver.
Baseline copied from imx_3.14.y branch.Signed-off-by: Sandor Yu
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- enable pcie on imx6qdl sabreauto boards.
Signed-off-by: Richard Zhu
(cherry picked from commit 21c4323d54ec3a25bb73deb98d23ddd1bb3c6c03) -
We may meet the following errors with a SD3.0 DDR50 cards during reboot test.
mmc0: new ultra high speed DDR50 SDHC card at address aaaa
mmcblk0: mmc0:aaaa SU08G 7.40 GiB
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00
mmcblk0: retrying using single block read
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 0
.....
Buffer I/O error on device mmcblk0, logical block 0
mmcblk0: unable to read partition tableThe root cause is still unknown.
Since there's an errata of Sandisk eMMC card before that it requires delay for CMD6
for eMMC DDR mode to work stable, we also suspect the SD3.0 DDR requires similar delay.
(Still not confirmed by Sandisk)
By adding the delay, the overnight reboot test(run 2000+ times) did not
show the issue anymore. Originally it can easy show the error after about 20 times of
reboot test.So this patch would be the temporary workaround for Sandisk SD3.0 DDR50 mode
unstable issue.Signed-off-by: Dong Aisheng
(cherry picked from commit ef3bce5feb2ed36c9f4483287454d35ae330dbe3)
(cherry picked from commit c0cbde8a248036fae1768f232385290c23eddbd7)
(cherry picked from commit 138bab9f78ea2285b6e7c7cd6c8cd956def44003)
(cherry picked from commit 12d7e80e7505027feed3eb1ee6d037b1e6df249b)
Signed-off-by: Haibo Chen -
After adding mega fast support, the default enabled usdhc wakeup will block
M/F to gate off power domain.
To avoid this issue, we only claim wakeup capability and reply on user to enable
it via sysfs according to real needs.
The drawback of such change is that for SDIO WiFi Wakeup On Wireless feature,
User has to enable both uSDHC and WiFi WoW wakeup mannually to make
WoW work well.BTW, due to the wakeup feature is controller itself, so we do not need to reply
on WiFi PM flags to enable it.Signed-off-by: Dong Aisheng
(cherry picked from commit 58f91ff6f6719fef44f5122ae1d8a5df7e0061d5)
Signed-off-by: Haibo ChenConflicts:
drivers/mmc/host/sdhci-esdhc-imx.c -
The usdhc of i.MX6Q/DL can work well under low power mode without
request high bus freq. So we do not need request bus freq for i.MX6Q/DL.
It can save power for i.MX6D/DL due to it saves a lot busfreq switch
cost as well as the CPU time runing on high bus freq after switch
during low power mode.A new flag ESDHC_FLAG_BUSFREQ is added to indicated this requirement.
Currently only i.MX6SL is using it.Signed-off-by: Dong Aisheng
(cherry picked from commit 3b954ce55b56dfce195d65b84913ff3c0fcb9f82)
Signed-off-by: Haibo ChenConflicts:
drivers/mmc/host/sdhci-esdhc-imx.c -
Do not need to enable the controller card cd interrupt wakeup
if using GPIO as card detect since it's meaningless.Signed-off-by: Dong Aisheng
(cherry picked from commit e66bb4978fe4b4fb96e81a1a083c16f84f5aa710)
Signed-off-by: Haibo Chen -
Except SDHCI_QUIRK_BROKEN_CARD_DETECTION and MMC_CAP_NONREMOVABLE,
we also do not need to handle controller native card detect interrupt
for gpio as card detect case.
If we wrong enabled the card detect interrupt for gpio case,
it will cause a lot of unexpected card detect interrupts during data transfer
which should not happen.Signed-off-by: Dong Aisheng
(cherry picked from commit 2bf47f78bee173798e6d6f360b12defd945c936c)
Signed-off-by: Haibo ChenConflicts:
drivers/mmc/host/sdhci.c -
Request BUS_FREQ_HIGH when bus is busy and then release BUS_FREQ_HIGH
when bus becomes idle.Signed-off-by: Dong Aisheng
(cherry picked from commit 64994f7115573c9ede53b51536b2c15f7cf0112a)
Signed-off-by: Haibo ChenConflicts:
drivers/mmc/host/sdhci-esdhc-imx.c -
- Some sandisk emmc cards need certain delay befor sending cmd13 after cmd6.
Original CR: ENGR174296 (commit: fd031f9)Acked-by: Aisheng Dong
Signed-off-by: Ryan QIAN
(cherry picked from commit f942bf1db36355d46f38792601594949f3f2c71b)
Signed-off-by: Haibo ChenConflicts:
drivers/mmc/core/mmc_ops.c -
According to the help text in the config SWP_EMULATE in arch/arm/mm/Kconfig:
"In some older versions of glibc [
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Broadcom WiFi requires reset by operating wlreg_on regulator
when doing insmod/rmmod.
Keep wlreg_on will cause card state wrong and unable to re-insmod.Signed-off-by: Dong Aisheng
(cherry picked from commit d65683e1d0717fa039ebd4c55562e6ee745354b7)
Signed-off-by: Haibo Chen -
The card detect of Broadcom WiFi on uSDHC2 port can not function
well with a non-removalbe card. Because MMC core only enumerate
one time for non-removable card which is not work for Broadcom WiFI.
So remove it.Signed-off-by: Dong Aisheng
(cherry picked from commit ed4c1c749c755839775ff4ad2078e659fec18650)
Signed-off-by: Haibo ChenConflicts:
arch/arm/boot/dts/imx7d-sdb.dts -
There's a Broadcom WiFi on usdhc2.
Add this property due to Broadcom WiFi driver needs call wifi_card_detect
function.Signed-off-by: Dong Aisheng
(cherry picked from commit 72015985537b5bd14ac7b0c97860ab26309ad1a1)
Signed-off-by: Haibo Chen -
WiFi driver could call wifi_card_detect function to re-detect card,
this is required by some special WiFi cards like broadcom WiFi.
To use this function, a new property is introduced to indicate a wifi host.Signed-off-by: Dong Aisheng
(cherry picked from commit 74e71dd0aebb9e931f02aefa3dd1990cbe642ae4)
Signed-off-by: Haibo ChenConflicts:
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt -
Add Broadcom WiFi chip BCM4339 on board support.
Need adds a bcmdhd_wlan@0 node for WiFi driver to probe properly.Signed-off-by: Dong Aisheng
(cherry picked from commit 24b44a415df9a27036b843284a179448dcc5fe20)
Signed-off-by: Haibo ChenConflicts:
arch/arm/boot/dts/imx7d-sdb.dts -
In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.Instead of setting the PRE_CTRL register any time we want to do on-the-fly
switch(PRE keeps working before and after the switch), we change to set the
register in the on-the-fly configuration interrupt(EOF) handler. This way,
we may avoid encountering the problematic PRE automatic writing cycle for sure.Signed-off-by: Liu Ying
(cherry picked from commit 6218cbcf34f5fb7910a824a8d31cc58819d0bd00) -
In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.The software mechanism to set the PRE_CTRL register is different for PRE Y
resolution higher than 9 lines and lower than or equal to 9 lines.For cases in which Y resolution is higher than 9 lines, before we update PRE
shadow, we just need to wait until the PRE store engine status runs out of
the problematic PRE automatic writing window.While for cases in which Y resolutin is lower than or equal to 9 lines, we
have to update PRE shadow in the buffer flip interrupt handler.Signed-off-by: Liu Ying
(cherry picked from commit bd9c14e24aaf67926dfd31bd819ab0c87129fe4b) -
In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.The software mechanism to set the PRE_CTRL register is different for PRE Y
resolution higher than 9 lines and lower than or equal to 9 lines. So,
this patch defines the small Y resolution and adds a helper to check the
Y resolution.Signed-off-by: Liu Ying
(cherry picked from commit cf7df46e3b1d2142ff354498982194247bf07fea) -
In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.This patch exports a function to set the PRE_CTRL register so that it could be
used by the software when the PRE automatic writing doesn't happen for sure.Signed-off-by: Liu Ying
(cherry picked from commit e64bbcd9243a17f9eba9cb3abb6f2c1939eae110) -
There could be frame drop issue when we do pan display if we update PRE next
buffer address before waiting for the flip completion, because we may hold
the flip completion already and then two continuous pan display operations may
happen quickly within one active period of frame scanning - the first PRE next
buffer address is overriden. To fix this issue, this patch updates the buffer
address after the flip completion.Signed-off-by: Liu Ying
(cherry picked from commit d0126e42f46f6dad9ae8c6aa390b0e1bea76492e) -
LVDS0 can not work on imx6q auto and SDB board,
it is caused by ldb0 clock setting is missed in ipu driver.Signed-off-by: Sandor Yu
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Add pinctrl sleep mode support for usdhc, and enable usdhc in lpsr mode.
Signed-off-by: Haibo Chen
(cherry picked from commit 75b33d1a578abaed44b11a05187c19dedb25aad2)Conflicts:
arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts -
For LPSR mode, usdhc iomux settings will be lost after resume,
so add pinctrl sleep mode support.Signed-off-by: Haibo Chen
(cherry picked from commit 983a7a174ed20d34a170a6aba70ff9d5bb2c9973)