07 Oct, 2008
1 commit
03 Oct, 2008
4 commits
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Add a defconfig for the AMCC Arches evaluation board
Signed-off-by: Victor Gallardo
Signed-off-by: Josh Boyer -
Basic functionality for the AMCC Arches eval Board.
Signed-off-by: Victor Gallardo
Signed-off-by: Josh Boyer -
The Arches Evaluation board is based on the AMCC 460GT SoC chip.
This board is a dual processor board with each processor providing
independent resources for Rapid IO, Gigabit Ethernet, and serial
communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH,
UART, EEPROM and temperature sensor, along with a shared debug port.
The two 460GT's will communicate with each other via shared memory,
Gigabit Ethernet and x1 PCI-Express.Signed-off-by: Victor Gallardo
Signed-off-by: Josh Boyer -
Add support for the phy types found on the Arches and other
PowerPC 460 based boards.Signed-off-by: Victor Gallardo
Acked-by: Benjamin Herrenschmidt
Acked-by: Jeff Garzik
Signed-off-by: Josh Boyer
02 Oct, 2008
3 commits
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This patch allows the 4xx (conventional) PCI bridge to be disabled
via the device tree. This is needed for 4xx PCI adapter hardware.Use the PCI node's status property to disable the PCI bridge.
Signed-off-by: Matthias Fuchs
Acked-by: Stefan Roese
Signed-off-by: Josh Boyer
01 Oct, 2008
1 commit
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The math emulation code is centered around a set of generic macros that
provide the core of the emulation that are shared by the various
architectures and other projects (like glibc). Each arch implements its
own sfp-machine.h to specific various arch specific details.For historic reasons that are now lost the powerpc math-emu code had
its own version of the common headers. This moves us to using the
kernel generic version and thus getting fixes when those are updated.Also cleaned up exception/error reporting from the FP emulation functions.
Signed-off-by: Kumar Gala
30 Sep, 2008
3 commits
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The PowerPC 405EZ SoC has some differences in the interrupt layout and
handling for the MAL. The SERR, TXDE, and RXDE interrupts are OR'd into
a single interrupt. Also, due to the possibility for interrupt coalescing,
the TXEOB and RXEOB interrupts require an interrupt bit to be cleared in
the ICINTSTAT SDR.This sets the proper MAL feature bits for 405EZ boards, and adds a common
shared handler for SERR, TXDE, and RXDE. The defines for the ICINTSTAT DCR
are added to the proper header file as well.This has been adapted from code originally written by Stefan Roese.
Signed-off-by: Josh Boyer
Acked-by: Benjamin Herrenschmidt
Acked-by: Jeff Garzik
Signed-off-by: Josh Boyer -
There are some PowerPC SoCs that do odd things with the MAL handling. In
order to accommodate them, we need to introduce a feature mechanism that is
similar to the existing emac_has_feature function.This adds a feature variable to the mal_instance structure, and adds a
mal_has_feature function. Two features are defined and are guarded
by Kconfig options that are selected by the affected platforms.MAL_FTR_CLEAR_ICINSTAT is used for platforms that need to clear the
interrupt bits in the ICINTSTAT SDR for txeob/rxeob. This is common
on MAL implementations that have interrupt coalescing.MAL_FTR_COMMON_ERR_INT is used for platforms that have SERR, TXDE,
and RXDE OR'd into a single interrupt bit.Signed-off-by: Josh Boyer
Acked-by: Benjamin Herrenschmidt
Acked-by: Jeff Garzik
Signed-off-by: Josh Boyer -
Some PowerPC 40x chips have errata that force us not to use the integrated
flow control. We have the feature defined, but it currently can't be used
because it is never added to EMAC_FTRS_POSSIBLE.This adds a Kconfig option for affected platforms to select and puts the
feature in the EMAC_FTRS_POSSIBLE list. This is set for PowerPC 405EZ
platforms as well.Signed-off-by: Josh Boyer
Acked-by: Benjamin Herrenschmidt
Acked-by: Jeff Garzik
Signed-off-by: Josh Boyer
29 Sep, 2008
3 commits
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Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC
MPC8641D).Fixup to correctly reconfigure USB, provided by an NEC uPD720101, after
device is reset. This requires a set of chip specific registers in the
devices configuration space to be correctly written, enabling all ports
and switching the device to use an external 48-MHz Oscillator.Signed-off-by: Martyn Welch
Signed-off-by: Kumar Gala -
For many of the embedded boards, "model" and "Machine" are printing
the same thing; remove the redundant code and allow the generic
show_cpuinfo to print the model information.Signed-off-by: Becky Bruce
Acked-by: Paul Gortmaker
Acked-by: Martyn Welch
Signed-off-by: Kumar Gala -
mpc83xx_wdt is the OF driver now, so we don't need fsl_soc constructor.
Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala
25 Sep, 2008
10 commits
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Now that arch/ppc is gone we don't need CONFIG_PPC_MERGE anymore
remove the dead code associated with !CONFIG_PPC_MERGE.Signed-off-by: Kumar Gala
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This rearranges a bit of code, and adds support for
36-bit physical addressing for configs that use a
hashed page table. The 36b physical support is not
enabled by default on any config - it must be
explicitly enabled via the config system.This patch *only* expands the page table code to accomodate
large physical addresses on 32-bit systems and enables the
PHYS_64BIT config option for 86xx. It does *not*
allow you to boot a board with more than about 3.5GB of
RAM - for that, SWIOTLB support is also required (and
coming soon).Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala -
Implement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will
be used by the fast get_user_pages() to differenciate PTEs that correspond
to a valid struct page from special mappings that don't such as IO mappings
obtained via io_remap_pfn_ranges().We currently only implement this on sub-arch that support SMP or will so
in the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).Signed-off-by: Kumar Gala
Acked-by: Benjamin Herrenschmidt -
There are some minor issues with support 64-bit PTEs on a 32-bit processor
when dealing with SMP.* We need to order the stores in set_pte_at to make sure the flag word
is set second.
* Change pte_clear to use pte_update so only the flag word is cleared
* Added a WARN_ON to set_pte_at to ensure the pte isn't present for
the 64-bit pte/SMP case (to ensure our assumption of this fact).Signed-off-by: Kumar Gala
Acked-by: Becky Bruce -
Introduced a new set of low level tlb invalidate functions that do not
broadcast invalidates on the bus:_tlbil_all - invalidate all
_tlbil_pid - invalidate based on process id (or mm context)
_tlbil_va - invalidate based on virtual address (ea + pid)On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and
_tlbil_va should be functionally equivalent to _tlbie.The intent of this change is to handle SMP based invalidates via IPIs instead
of broadcasts as the mechanism scales better for larger number of cores.On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls
and tlbsx/tlbwe for invalidate virtual address.Signed-off-by: Kumar Gala
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Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala -
We essentially adopt the 64-bit dma code, with some changes to support
32-bit systems, including HIGHMEM. dma functions on 32-bit are now
invoked via accessor functions which call the correct op for a device based
on archdata dma_ops. If there is no archdata dma_ops, this defaults
to dma_direct_ops.In addition, the dma_map/unmap_page functions are added to dma_ops
because we can't just fall back on map/unmap_single when HIGHMEM is
enabled. In the case of dma_direct_*, we stop using map/unmap_single
and just use the page version - this saves a lot of ugly
ifdeffing. We leave map/unmap_single in the dma_ops definition,
though, because they are needed by the iommu code, which does not
implement map/unmap_page. Ideally, going forward, we will completely
eliminate map/unmap_single and just have map/unmap_page, if it's
workable for 64-bit.Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala -
Use the struct device's numa_node instead; use accessor functions
to get/set numa_node.Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala -
32-bit platforms are about to start using dma.c; move the iommu
dma ops into their own file to make this a bit cleaner.Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala -
This is in preparation for the merge of the 32 and 64-bit
dma code in arch/powerpc.Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala
24 Sep, 2008
3 commits
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The initial patch had the option at the top level which wasn't
quite right. Moving under the platform options is a bit better.Signed-off-by: Kumar Gala
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Introduced a mpc86xx_defconfig that enables all 86xx boards and moved
all other 86xx related defconfigs under configs/86xx to match 83xx
and 85xx.Signed-off-by: Kumar Gala
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Signed-off-by: Kumar Gala
23 Sep, 2008
2 commits
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Now that arch/ppc is dead CONFIG_PPC_MERGE is always defined for all
powerpc platforms and we want to get rid of CONFIG_PPC_MERGE use
CONFIG_PPC instead.Signed-off-by: Kumar Gala
Acked-by: Benjamin Herrenschmidt
Cc: Paul Mackerras
Signed-off-by: Andrew Morton
Signed-off-by: Kumar Gala -
Structured similar to the existing QE GPIO support.
Signed-off-by: Peter Korsgaard
Acked-by: Anton Vorontsov
Signed-off-by: Kumar Gala
22 Sep, 2008
2 commits
20 Sep, 2008
2 commits
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We're currently passing NULL, and really shouldn't be.
Signed-off-by: Becky Bruce
Acked-By: Timur Tabi
Signed-off-by: Kumar Gala -
We need to create a false data dependency to ensure the loads of
the pte are done in the right order.Signed-off-by: Kumar Gala
19 Sep, 2008
1 commit
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arch/powerpc/kernel/sysfs.c:197:7: warning: "CONFIG_6xx" is not defined
arch/powerpc/kernel/sysfs.c:141: warning: 'run_on_cpu' defined but not usedSigned-off-by: Kumar Gala
18 Sep, 2008
1 commit
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Add the fsl,playback-dma and fsl,capture-dma properties to the Freescale
MPC8610 HPCD device tree. These properties connect the SSI nodes to the
DMA nodes for the DMA channels that the SSI should use. Also update the
ssi.txt documentation.These properties will be needed when the ASoC V2 version of the Freescale
MPC8610 device drivers are merged into the mainline.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
17 Sep, 2008
1 commit
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The CPM1 GPIO library code uses the non thread-safe clrbits32/setbits32
macros. This patch protects them with a spinlock.Based on the CPM2 patch from Laurent Pinchart ,
commit 639d64456e20cbfc866b18dc03cf9f9babc9c7cd.Signed-off-by: Jochen Friedrich
Signed-off-by: Kumar Gala
16 Sep, 2008
3 commits
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Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC
MPC8641D).This is the default config file for GE Fanuc's SBC610, a 6U single board
computer, based on Freescale's MPC8641D.Signed-off-by: Martyn Welch
Signed-off-by: Kumar Gala -
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC
MPC8641D).This is the basic board support for GE Fanuc's SBC610, a 6U single board
computer, based on Freescale's MPC8641D.Signed-off-by: Martyn Welch
Signed-off-by: Kumar Gala -
This is just a parallel of a5dc66e2ab2e2cf641346b056a69a67cfcf9458c
applied to the sbc8560 board.Signed-off-by: Paul Gortmaker
Signed-off-by: Kumar Gala
