28 Sep, 2010
1 commit
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* master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits)
ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tile
ARM: 6409/1: davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE
ARM: 6408/1: omap: Map only available sram memory
ARM: 6407/1: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries
ARM: pxa: remove pr_ uses of KERN_
ARM: pxa168fb: clear enable bit when not active
ARM: pxa: fix cpu_is_pxa*() not expanding to zero when not configured
ARM: pxa168: fix corrected reset vector
ARM: pxa: Use PIO for PI2C communication on Palm27x
ARM: pxa: Fix Vpac270 gpio_power for MMC
ARM: 6401/1: plug a race in the alignment trap handler
ARM: 6406/1: at91sam9g45: fix i2c bus speed
leds: leds-ns2: fix locking
ARM: dove: fix __io() definition to use bus based offset
dmaengine: fix interrupt clearing for mv_xor
ARM: kirkwood: Unbreak PCIe I/O port
ARM: Fix build error when using KCONFIG_CONFIG
ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasing
ARM: 6400/1: at91: fix arch_gettimeoffset fallout
ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARM
...
27 Sep, 2010
1 commit
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The PL310 on the ct-ca9x4 tile for the Versatile Express does not need
to add additional latency when accessing its cache RAMs. Unfortunately,
the boot monitor sets this up for an 8-cycle delay on reads and writes,
resulting in greatly reduced memory performance when the L2 cache is
enabled.This patch sets the L2 RAM latencies to the correct value of 1 cycle
on the ct-ca9x4 tile before enabling the L2 cache.Acked-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Russell King
25 Sep, 2010
9 commits
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On Davinci SRAM is mapped as MT_DEVICE becasue of the section
mapping pre-requisite instead of intended MT_MEMORY_NONCACHEDSince the section mapping limitation gets fixed with first
patch in this series, the MT_MEMORY_NONCACHED can be used now.Signed-off-by: Santosh Shilimkar
Acked-by: Kevin Hilman
Signed-off-by: Russell King -
Currently we map 1 MB section while setting up SRAM on OMAPs
Regardless of the actual memory. The physical OCM RAM available
on OMAP SOCs is in order of KBs. This patch maps only available
sram and cleans up some un-necessary cpu_is_xxx checks.Mapping un-available or non-accessible(secure) memory on the newer ARM
processor is dangerous. Because ARM CPUs can now speculatively prefetch,
we should avoid mapping any no-existing or secure memory.Signed-off-by: Santosh Shilimkar
Acked-by: Tony Lindgren
Signed-off-by: Russell King -
This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED
types so that at boot-up, we can map memories outside system memory
at page level granularityPreviously the mapping was limiting to section level, which creates
unnecessary additional mapping for which physical memory may not
present. On the newer ARM with speculation, this is dangerous and can
result in untraceable aborts.Signed-off-by: Santosh Shilimkar
Signed-off-by: Russell King -
Signed-off-by: Joe Perches
Signed-off-by: Eric Miao -
When CONFIG_PXA3xx is not selected, cpu_is_pxa3xx() doesn't expand to
zero, which in some places doesn't result in correct optimization.Signed-off-by: Eric Miao
Reported-and-tested-by: Marek Vasut -
Reset vector for pxa168 is 0xffff_0000 not 0x0. This fix allows
reboot to workSigned-off-by: Mark F. Brown
Signed-off-by: Eric Miao -
Original idea by: Mike Rapoport
Signed-off-by: Marek Vasut -
GPIO 0 is valid, yet this platform doesn't have any power GPIO for MMC.
Signed-off-by: Marek Vasut
23 Sep, 2010
4 commits
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When the policy for user space is to ignore misaligned accesses from user
space, the processor then performs a documented rotation on the accessed
data. This is the result of the access being trapped, and the kernel
disabling the alignment trap before returning to user space again.In kernel space we always want misaligned accesses to be fixed up. This
is enforced by always re-enabling the alignment trap on every entry into
kernel space from user space. No such re-enabling is performed when an
exception occurs while already in kernel space as the alignment trap is
always supposed to be enabled in that case.There is however a small race window when a misaligned access in user
space is trapped and the alignment trap disabled, but the CPU didn't
return to user space just yet. Any exception would be entered from kernel
space at that point and the kernel would then execute with the alignment
trap disabled.Thanks to Maxime Bizon for providing a test module
that made this issue reproducible.Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King -
Use a correct udelay value to get bus speed around 100KHz. The udelay
value was most likely copied from the older devices, but the 9g45
is signicantly faster (400MHz, DDR, ..), so a udelay of 2 gives a
bus speed of around 190KHz, which is too fast for some devices.
A udelay value of 5 gives a bus speed of around 90KHz here.Signed-off-by: Peter Korsgaard
Signed-off-by: Nicolas Ferre
Signed-off-by: Russell King -
This fixes the regression caused by the commit 6fee48cd330c68
("dma-mapping: arm: use generic pci_set_dma_mask and
pci_set_consistent_dma_mask").ARM needs to clip the dma coherent mask for dmabounce devices. This
restores the old trick.Note that strictly speaking, the DMA API doesn't allow architectures to do
such but I'm not sure it's worth adding the new API to set the dma mask
that allows architectures to clip it.Reported-by: Krzysztof Halasa
Signed-off-by: FUJITA Tomonori
Acked-by: Russell King
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
20 Sep, 2010
3 commits
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Signed-off-by: Eric Miao
Acked-by: Saeed Bishara
Signed-off-by: Nicolas Pitre -
The support for the 2 pcie port of the 6282 has broken i/o port by switching
*_IO_PHYS_BASE and *_IO_BUS_BASE. In fact, the patches reintroduced the same
bug solved by commit 35f029e2514be209eb0e88c7d927f3bcc42a5cc2.
So, I'm adding back *_IO_BUS_BASE in resource declaration and fix definition
of KIRKWOOD_PCIE1_IO_BUS_BASE. With this change, the xgi card on my t5325 is
working again.Signed-off-by: Arnaud Patard
Acked-by: Saeed Bishara
Signed-off-by: Nicolas Pitre
Cc: stable@kernel.org -
…git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410
ARM: S3C64XX: Fix coding style errors on mach-real6410
ARM: S3C64XX: Prototype SPI devices
ARM: S3C64XX: Fix dev-spi build
ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstr
ARM: SAMSUNG: Fix on drive strength value
ARM: S5PV210: Add FIMC clocks
ARM: S5PV210: Reduce the iodesc length of systimer
ARM: S5PV210: Update I2C-1 Clock Register Property.
ARM: S5P: Decrease IO Registers memory region size on FIMC
ARM: S5P: Fix DMA coherent mask for FIMC
19 Sep, 2010
3 commits
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Jonathan Cameron reports that when using the environment
variable KCONFIG_CONFIG, he encounters this error:make[2]: *** No rule to make target `.config', needed by `arch/arm/boot/compressed/vmlinux.lds'
Reported-by: Jonathan Cameron
Signed-off-by: Russell King -
ARMv7 onwards requires that there are no aliases to the same physical
location using different memory types (i.e. Normal vs Strongly Ordered).
Access to SO mappings when the unaligned accesses are handled in
hardware is also Unpredictable (pgprot_noncached() mappings in user
space).The /dev/mem driver requires uncached mappings with O_SYNC. The patch
implements the phys_mem_access_prot() function which generates Strongly
Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and
Normal Noncacheable (writecombine) if O_SYNC.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King -
5cfc8ee0bb51 (ARM: convert arm to arch_gettimeoffset()) marked all of
at91 AND at91x40 as needing ARCH_USES_GETTIMEOFFSET, and hence no high
res timer support / accurate clock_gettime() - But only at91x40 needs it.Cc: stable@kernel.org
Signed-off-by: Peter Korsgaard
Acked-by: John Stultz
Acked-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Russell King
18 Sep, 2010
4 commits
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Add IORESOURCE_IRQ_HIGHLEVEL irq flag to dm9000 driver
platform data in board mach-real6410.Signed-off-by: Darius Augulis
[kgene.kim@samsung.com: minor title fix]
Signed-off-by: Kukjin Kim -
Fix errors reported by checkpatch.pl script
Signed-off-by: Darius Augulis
[kgene.kim@samsung.com: minor title fix]
Signed-off-by: Kukjin Kim -
Avoids build warnings due to the undeclared non-statics.
Signed-off-by: Mark Brown
Signed-off-by: Kukjin Kim -
If a signal hits us outside of a syscall and another gets delivered
when we are in sigreturn (e.g. because it had been in sa_mask for
the first one and got sent to us while we'd been in the first handler),
we have a chance of returning from the second handler to location one
insn prior to where we ought to return. If r0 happens to contain -513
(-ERESTARTNOINTR), sigreturn will get confused into doing restart
syscall song and dance.Incredible joy to debug, since it manifests as random, infrequent and
very hard to reproduce double execution of instructions in userland
code...The fix is simple - mark it "don't bother with restarts" in wrapper,
i.e. set r8 to 0 in sys_sigreturn and sys_rt_sigreturn wrappers,
suppressing the syscall restart handling on return from these guys.
They can't legitimately return a restart-worthy error anyway.Testcase:
#include
#include
#include
#include
#includevoid f(int n)
{
__asm__ __volatile__(
"ldr r0, [%0]\n"
"b 1f\n"
"b 2f\n"
"1:b .\n"
"2:\n" : : "r"(&n));
}void handler1(int sig) { }
void handler2(int sig) { raise(1); }
void handler3(int sig) { exit(0); }main()
{
struct sigaction s = {.sa_handler = handler2};
struct itimerval t1 = { .it_value = {1} };
struct itimerval t2 = { .it_value = {2} };signal(1, handler1);
sigemptyset(&s.sa_mask);
sigaddset(&s.sa_mask, 1);
sigaction(SIGALRM, &s, NULL);signal(SIGVTALRM, handler3);
setitimer(ITIMER_REAL, &t1, NULL);
setitimer(ITIMER_VIRTUAL, &t2, NULL);f(-513); /* -ERESTARTNOINTR */
write(1, "buggered\n", 9);
return 1;
}Signed-off-by: Al Viro
Acked-by: Russell King
Cc: stable@kernel.org
Signed-off-by: Linus Torvalds
17 Sep, 2010
9 commits
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Setting of these bits can cause issues on other SMP SoC's not produced
by ARM.Acked-by: Catalin Marinas
Signed-off-by: Daniel Walker
Signed-off-by: Russell King -
Al Viro reports that calling "sys_sigsuspend(-ERESTARTNOHAND, 0, 0)"
with two signals coming and being handled in kernel space results
in the syscall restart being done twice.Avoid this by clearing the 'why' flag when we call the signal handling
code to prevent further syscall restarts after the first.Acked-by: Al Viro
Signed-off-by: Russell King -
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.Cc: Nicolas Pitre
Cc:
Signed-off-by: Catalin Marinas
Signed-off-by: Russell King -
On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption
can occur if a shared cache line is replaced on one CPU as another CPU
is accessing it.This workaround sets two bits in the diagnostic register of the Cortex-A9,
reducing the linefill issuing capabilities of the processor and
avoiding the erroneous behaviour.Acked-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Russell King -
On versions of the Cortex-A9 up to and including r2p2, under rare
circumstances, a DMB instruction between 2 write operations may not
ensure the correct visibility ordering of the 2 writes.This workaround sets a bit in the diagnostic register of the Cortex-A9,
causing the DMB instruction to behave like a DSB, which functions
correctly on the affected cores.Acked-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Russell King -
Kconfig doesn't have any knowledge of specific v7 cores, so it is possible
to select errata workarounds that may cause inadvertent behaviour when
executed on a core other than those targetted by the fix.This patch improves the variant and revision checking in proc-v7.S so
that the primary part number is also considered when applying errata
workarounds.Acked-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Russell King -
We have to use _cansleep gpio accessors in the MMCI driver so as
to avoid slowpath warnings, now U300 has MMCI but doesn't have
these functions in place to siply wrap the existing non-sleeping
functions into sleepable variants.Signed-off-by: Linus Walleij
Signed-off-by: Russell King -
The prescaler 16 is now used only when the timer runs at 32 MHz
or more. Some comment updates as well.Acked-by: Alessandro Rubini
Signed-off-by: Jonas Aaberg
Signed-off-by: Linus Walleij
Signed-off-by: Russell King -
timer0 to 3 are all on mtu block 0, so don't calculate the clock event
rate based upon mtu block 1's clock speed.Acked-by: Alessandro Rubini
Signed-off-by: Jonas Aaberg
Signed-off-by: Linus Walleij
Signed-off-by: Russell King
14 Sep, 2010
6 commits
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The irqs.h usage here got missed in the Samsung platform reorganisation.
Signed-off-by: Mark Brown
Acked-by: Jassi Brar
Signed-off-by: Kukjin Kim -
This patch fixes bug on gpio drive strength helper function.
The offset should be like follwoing.
- off = chip->chip.base - pin;
+ off = pin - chip->chip.base;In the s5p_gpio_get_drvstr(),
the second line is unnecessary, because overwrite drvstr.
drvstr = __raw_readl(reg);
- drvstr = 0xffff & (0x3 << shift);And need 2bit masking before return the drvstr value.
drvstr = drvstr >> shift;
+ drvstr &= 0x3;In the s5p_gpio_set_drvstr(), need relevant bit clear.
tmp = __raw_readl(reg);
+ tmp &= ~(0x3 << shift);
tmp |= drvstr << shift;Reported-by: Jaecheol Lee
Signed-off-by: Kukjin Kim -
This patch fixes on defined drive strength value for GPIO.
According to data sheet, if we want drive strength 1x, the value
should be 00(b), if 2x should be 10(b), if 3x should be 01(b),
and if 4x should be 11(b). Also fixes comment(from S5C to S5P).Reported-by: Janghyuck Kim
Signed-off-by: Kukjin Kim -
These clocks enables FIMC driver to operate on machines, which
bootloader power gated FIMC devices to save power on boot.Signed-off-by: Marek Szyprowski
Signed-off-by: Kyungmin Park
[kgene.kim@samsung.com: minor title fix]
Signed-off-by: Kukjin Kim -
It's enough to use 4KiB.
Signed-off-by: Kyungmin Park
Signed-off-by: Kukjin Kim -
CLK_GATE_IP3[8] is RESERVED. The port "I2C_HDMI_DDC" of CLK_GATE_IP3[10] is
used as another I2C port. Therefore, defined the unused I2C-1 as another I2C
there was left undefined but used.Signed-off-by: MyungJoo Ham
Signed-off-by: Kyungmin Park
Signed-off-by: Kukjin Kim
