14 Jun, 2014
1 commit
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Many A9 errata require bits in the diagnostic control register to be set.
During a suspend/resume cycle, the A9 core may get power gated, implying
that the register needs to be maintained across a suspend/resume cycle.
Also ensure that power control register is saved/restored.Signed-off-by: Ranjani Vaidyanathan
05 Jun, 2014
1 commit
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Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the
IRAM page table. We need to ensure that both the DDR and IRAM page
table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible. Only the WFI and suspend code that puts DDR into self-refresh
is located in this 8k. The DDR frequency code that also puts the DDR into
self-refresh need not be located in this 8K region. Currently this patch
allocates a separate 4K region in IRAM for the DDR frequency change code.Additional conditions to be met:
1. Disable L2 when DDR is in self-refresh.
2. Ensure that L1 and branch prediction are disabled when we
are switching to IRAM page tables, based on recommendation from
ARM.This patch also dynamically calculate size of all the code that puts
DDR into self-refresh (low power and ddr freq change).Signed-off-by: Ranjani Vaidyanathan
31 May, 2014
1 commit
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Cpufreq code:
1. Busfreq can be dropped to 24MH only when CPU freq is at the lowest setpoint (396MHz). The
code was incorrectly releasing the request for high busfreq even when cpufreq was at 792MHz.
This caused incorrect pll2 behavior as the busfreq code expects CPUFREQ to be at 396MHz and
to be sourced from PLL2_PFD2_396M when the switch to low_bus_freq is requested.Clock code:
1. Ensure osc_clk usecount is also updated when pll2 or pll1 usecount is changed.
This fixes a debug warning message when CLK_DEBUG is enabled.Signed-off-by: Ranjani Vaidyanathan
21 May, 2014
1 commit
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The abnormal flow with the monkey test freeze problem is as below:
gckKERNEL_DestroyProcessDB--> aquire mutex --> gckCOMMAND_Detach(gckEVENT_FreeContiguousMemory) -->
___RemoveRecordFromProcessDB --> gckKERNEL_RemoveProcessDB --> aquire the same mutexthe fix is to disable mutex lock when perform record destory operations
Date: May 19, 2014
Signed-off-by: Xianzhong
Acked-by: Jason Liu
(cherry picked from commit 8d62ea9a655f1bb0ca86af222de7625abc8d2bc8)
09 May, 2014
10 commits
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mutex operation is performed in gckKERNEL_QueryProcessDB
remove spinlock for gckKERNEL_QueryProcessDB to avoid scheduling issueDate: May 08, 2014
Signed-off-by: Xianzhong
Acked-by: Jason Liu
(cherry picked from commit 554581201c0a1c2c7caddad5750b1fd678e09c8c) -
Vivante patch name:
fix_fsl_2d_base_on_p13.v2.rls.diff-Updated the outstanding request limit to 12.
-Refined the 2D chip feature check.
-Refine the 2D cache flush operation
(avoid FE and PE access memory through the same port).
-Enable cache flush for filterblt.
-Dynamic enabling SPLIT_RECT by checking chip feature(disable for us)
-Use brush stretch blt for clear operation.
-Enable SplitFilterBlit to workaround the 2d hang issue in filterblit case.
-Refine 2d line operation.Date: May 05, 2014
Signed-off-by: Loren Huang
Acked-by: Shawn Guo -
the potential risk is found in special case when application exit,
deleting record will cause the unexpected issue when process database is destoryed without atom protectionthe enhanced database patch should be applied to avoid the unexpected kernel issue
Date: Apr 17, 2014
Signed-off-by: Xianzhong
Acked-by: Jason Liu
(cherry picked from commit e799c1ae023264c0e1e1e41d448e30e2304944e1) -
this patch can fix NULL pointer issue in GPU kernel driver with the following log
[] (gckEVENT_AddList+0x0/0x810 [galcore]) from [] (gckCOMMAND_Commit+0xf28/0x118c [galcore])
[] (gckCOMMAND_Commit+0x0/0x118c [galcore]) from [] (gckKERNEL_Dispatch+0x120c/0x24e4 [galcore])
[] (gckKERNEL_Dispatch+0x0/0x24e4 [galcore]) from [] (drv_ioctl+0x390/0x540 [galcore])
[] (drv_ioctl+0x0/0x540 [galcore]) from [] (vfs_ioctl+0x30/0x44)The false code is at 0x217bc where the 0-pointer happens (r3 = 0)
gcuVIDMEM_NODE_PTR node = (gcuVIDMEM_NODE_PTR)(gcmUINT64_TO_PTR(Record->info.u.FreeVideoMemory.node));
217b8: e5953028 ldr r3, [r5, #40] ; 0x28if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
217bc: e5932000 ldr r2, [r3]
217c0: e5922000 ldr r2, [r2]
217c4: e152000a cmp r2, sl
{
gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(Event->kernel,Date: Apr 23, 2014
Signed-off-by: Xianzhong
Acked-by: Jason Liu
(cherry picked from commit fcde214d8c793d4dd785e47175b5833f1f3f5f1f) -
Disable GPU auto recovery so that GPU can dump the stack.
GPU support auto recovery function, when GPU meet some issue
it will try to do recovery, but most of cases GPU can't really
recovery, we do find some cases GPU can recovery for example
some 2D hang, but customer is not accept such recovery, so show
the GPU stack dump and find the root cause is the correct way.Date: Apr 24, 2014
Signed-off-by: Richard Liu
(cherry picked from commit 888c79ab0f114b7b259266fc82c1399cbb926faf) -
Vivante patch name:000e-more-refinements-for-wclip-issue
Date: Apr 14, 2014
Signed-off-by: Loren Huang
Acked-by: Shawn Guo -
Vivante patch name:0002-more-refinements-for-wclip-issue
Date: Apr 14, 2014
Signed-off-by: Loren Huang
Acked-by: Shawn Guo -
Vivante patch name:0001-more-refinements-for-wclip-issue
Date: Apr 14, 2014
Signed-off-by: Loren Huang
Acked-by: Shawn Guo -
Access GPU register will cause system hang(bus lock-up) without log when clock is off,
GPU kernel BUG_ON is added to check if GPU clock is off when read & write GPU registers,GPU clock issue can be easily identified with the detailed kernel panic log as below:
kernel BUG at drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c:2423!
Unable to handle kernel NULL pointer dereference at virtual address 0000000
...
[] (__bug+0x1c/0x28) from [] (gckOS_ReadRegisterEx+0xbc/0xdc)
[] (gckOS_ReadRegisterEx+0xbc/0xdc) from [] (gckHARDWARE_QueryIdle+0x4c/0xbc)
[] (gckHARDWARE_QueryIdle+0x4c/0xbc) from [] (_TryToIdleGPU+0x70/0x12c)Mutex protection is not necessary for interrupt handling, because GPU clock is only turned off
by interrupt worker thread during clock gating.Date: Apr 11, 2014
Signed-off-by: Xianzhong
Acked-by: Jason Liu
(cherry picked from commit 50c3767eb19bb22f395215755dac220f4bbb2f14) -
Code is sync to
232293e0abb46639e188ab9d8643f1dbf94534f6* ENGR00306992 Revert "ENGR00302036-3 [#1078]gpu2d may cause bus hang in
* some corner case"Date: May 09,2014
Signed-off-by: Loren Huang
Acked-by: Shawn Guo
01 Apr, 2014
1 commit
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These are Category B, hence workaround is essential.
Signed-off-by: Nitin Garg
04 Mar, 2014
2 commits
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Add DDR3 support for MX6SL
Signed-off-by: Grace Si
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Use different MMDC parameters for 100M and 24M of i.MX6SL LPDDR2
Signed-off-by: Grace Si
27 Feb, 2014
2 commits
-
Signed-off-by: Eli Billauer
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For more information about Xillybus, see http://xillybus.com
Signed-off-by: Eli Billauer
13 Feb, 2014
2 commits
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- add one imx pcie ep simple skeleton driver to demo
the msi trigger capability in imx6 pcie rc/ep validation
systemTest howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
root@sabresd_6dq:/ #- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
496: 1 0 0 0 PCIe-MSI- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
496: 2 0 0 0 PCIe-MSISigned-off-by: Richard Zhu
-
- setup one new outbound memory region at rc side, used
to let imx6 pcie rc can access the memory of imx6 pcie ep
in imx6 pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
- change the test region size to be 15MB.NOTE:
- default address 0x4000_0000 of ep side would be
accessed in this demo.
Test howto:
step1:
EP side:
1.1:
echo 0x40000000 > /sys/devices/platform/imx-pcie/ep_bar0_addr1.2:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x400000000x40000000: EFE9EDF4 7583FB39 39EAFFEA FBDCFD78
step2:
RC side:
memtool -32 0x01000000=58D454DA
memtool -32 0x01000004=7332095Bstep3:
EP side:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x400000000x40000000: 58D454DA 7332095B 39EAFFEA FBDCFD78
Signed-off-by: Richard Zhu
24 Jan, 2014
2 commits
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Ptp multicast packet receive does not work after Ethernet link is lost
for a short time and then reconnected again. Because fec call restart()
to reset all multicast when cable hotplug.
(cherry picked from commit adfa64f0c2bf35f8b902ae5700f97e7e11ae1794)Signed-off-by: Fugang Duan
(cherry picked from commit 57a3f0b6888dfa2a59c7f1b738badbec342b2d10) -
The timestamps generated in the i.MX drivers are generated by the
nanoseconds part coming from the 1588 clock. But the number of seconds
are maintained in a private structure of the interface. Those are
updated in a 1588 clock rollover interrupt.The timestamp is generated right before a rollover of a second and the
timestamp value is constructed afterwards. Therefore the bigger part of
the timestamp is wrong (the second).So, the patch Suggested solution (pseudo-code):
If( actual-time.nsec < timestamp.nsec &&
!FEC_IEVENT[TS_TIMER] )
Timestamp.sec = fpp->prtc -1;
Else
Timestamp.sec = fpp->prtc;(cherry picked from kernel 3.10.17
commit 430dc3830e80a749666f9eb2aa9feba55823c6eb)Signed-off-by: Fugang Duan
(cherry picked from commit 536d730bf2394bbe77e3256087b611477e0fc769)
23 Jan, 2014
3 commits
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- add sata phy cr(offset:0x7f3f) reset in sata resume to
workaround imx6q sata kinds of suspend resume link
issues.
- add sata phy cr reset during imx6q sata initialization,
to initialize the sata phy to be an initialized state.
- add about 100us delay between mpll_clk enable and cr-rst,
make sure that the mpll_clk is stable.
- add about 100us delay between cr-rst and waiting for rx_pll
stable too, make sure that the cr-rst is finished.
- make sure mpll_clk enable(bit1 of gpr13) is cleared,
before set it, otherwise, the sata phy link maybe failed
when some devices are used.
In order to level the compatibility:
- enable the ssc support(bit14 of gpr13)
- change the TX boost control(bit10~7) from 0dB to be the
default value 3.33dB.Signed-off-by: Richard Zhu
-
It is a ipu vdi driver bug, in vdi_split_process function
wrong base offset address is setting and video data will be
copy to wrong place in framebuffer.Correct the physical address to virtual address transfer and
add cache flush function, the issue is fixed.Signed-off-by: Sandor Yu
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Check the DMA status (DMA_IN_PROGRESS) is not strict enough, the two
TXs may also submit the DMA operation to the SDMA at the same time.
And the SDMA will hang at this case.This patch uses the bit operation to sync the DMA TX.
Also make it always wake up the process in the TX callback.
Signed-off-by: Huang Shijie
22 Jan, 2014
2 commits
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GPT Status register bit should be cleared by writing 1.
We do not need to read, modify, write for modifying the bits.
In Linux-3.0.35, while clearing ROV bit we inadvertently clear
other bit causing timer issues.Signed-off-by: Nitin Garg
-
The return of v2_set_next_event() will lead to an infinite loop in
tick_handle_oneshot_broadcast() - "goto again;" with imx6q WAIT mode
(to be enabled). This happens because when global event did not expire
any CPU local events, the broadcast device will be rearmed to a CPU
local next_event, which could be far away from now and result in a
max_delta_tick programming in set_next_event().Fix the problem by detecting those next events with increments larger
than 0x7fffffff, and simply return zero in that case.It leaves mx1_2_set_next_event() unchanged since only v2_set_next_event()
will be running with imx6q WAIT mode support.Thanks Russell King for helping understand the problem.
Signed-off-by: Shawn Guo
13 Dec, 2013
1 commit
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issue:
sata phy link down after suspend resume on imx6q TO1.3.
solution:
sata phy ref clock should be gated off/on in suspend/resumeSigned-off-by: Richard Zhu
06 Dec, 2013
2 commits
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This patch fix the Copyright issue introduced by commit: 2b94a4b
2b94a4b ENGR00290444: Need to update CAAM driver with SM patches from STC
The commit:2b94a4b wrongly change the Copyright:
- * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008, 2012-2013 Freescale Semiconductor, Inc.The correct one should be:
- * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.Signed-off-by: Jason Liu
-
For i.MX6DL, the latest datasheet defines the min voltage of VDDARM_CAP
for 996MHz setpoint is 1.25V, adding 25mV margin, so we should set the
VDDARM_CAP's voltage to 1.275V.Signed-off-by: Anson Huang
03 Dec, 2013
9 commits
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The platform hangs if UART 1 is not used a console on MX6 SABRESD.
The issue is because the UART UFCR register is not initialized and
the driver uses values provided by the bootloader (U-Boot in this
case). This patch initializes the UFCR register and does not rely
on the default or what is configured by the bootloader.Test method on MX6 SABRESD:
1. Add 'noconsole' to the kernel command line.
2. SSH to the board and type the below from the SSH window:
echo Hello >/dev/ttymxc0
3. Platform will hang, with the patch the hang will not be seen.Signed-off-by: Mahesh Mahadevan
(cherry picked from commit e1925c5b8ca74a77322f34772f170563fee76d0d) -
This patch adds logics to report video buffer field information
via VIDIOC_DQBUF ioctrl so that the user space may rely on this
to determine how to go on to process the dqueued video buffers.
Currently, we only support two field types - V4L2_FIELD_INTERLACED
and V4L2_FIELD_NONE.Signed-off-by: Liu Ying
-
According to datasheet, VDD_CACHE_CAP must not exceed VDDARM_CAP
by more than 200mV, as all of our i.MX6Q boards' VDD_CACHE_CAP
are connected to VDDSOC_CAP, so we need to follow this rule by
increasing VDDARM_CAP's voltage when necessary.Signed-off-by: Anson Huang
-
This patch updates IPUv3 IC RGB to YUV color space conversion
matrix's parameters to align with the default VIV GPU CSC
implementation so that we may pass relevant Android CTS test
cases.Signed-off-by: Liu Ying
(cherry picked from commit 17b6dbef8eea2051a6c3819f3690c21948bd0e93) -
Some boards' irq #125 are not pending, so we need to
force irq #32 to be pending manually to ensure CCM is
in correct stat before entering low power mode. Using
irq #32 is more reliable than #125, as we can trigger
it manually. See below commit for detail of CCM LPM
issue:commit 04b5224599fef16ef3a1856dd1b3205360b772c1
Signed-off-by: Anson Huang
-
V4L2_PIX_FMT_YUYV is the original format from camera and the source format
for CSI. This format may be needed on Android to do CSC before encoding.
We can now choose V4L2_PIX_FMT_YUYV, V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_RGB565
for the v4l capture format.Signed-off-by: Robby Cai
-
The ipu task thread checks outstanding tasks to be done on waiting
event uninterruptibly on the function find_task()'s return value.
However, sleeping on waiting event uninterruptibly contributes to
system load average value. This patch changes wait_event() to
wait_event_interruptible() to avoid the load average value inflation.Signed-off-by: Liu Ying
-
Previous ptp test environment is base on IPv4, now add VLAN
(virtual local area network) support. Fix the ptp packet parse
issue to support it.PTP test on VLAN environment:
- Enable kernel config "CONFIG_FEC_1588", and rebuild
- After kernel up, dhcp require IP address for eth0
- Use vconfig to add virtual netdev eth0.n (exp: eth0.5):
vconfig add eth0 5
- Use ifconfig to config virtual netdev eth5, and config
real netdev eth0 to 0.0.0.0:
ifconfig eth0.5 192.168.0.100 netmask 255.255.255.0 up
ifconfig eth0 0.0.0.0
- If connect switch, enable switch VLAN feature and add the
related ptp device ports to VID 5.
- Last, run the IXXAT stack V1.05.03:
ptp_main_1.05.03 -d -o -m -l -w -z -i 0:eth0.5Signed-off-by: Fugang Duan
-
The previous behavior of the driver did not work properly with Qt5
QtQuick multi touch-point gestures, due to how touch-points are
reported when removing a touch-point. My interpretation of the
available documentation [1] was that the driver should report all
touch-points between SYN_REPORTs, but it is not explicitly stated so.
I've found another mail-thread [2] where the creator of the protocol
states:"The protocol defines a generic way of sending a variable amount of
contacts. The contact count is obtained by counting the number of
non-empty finger packets between SYN_REPORT events."-Henrik RydbergI think this verifies my assumption that all touch-points should be
reported between SYN_REPORTs, otherwise it can not be used to obtain
the count.[1] https://www.kernel.org/doc/Documentation/input/multi-touch-protocol.txt
[2] http://lists.x.org/archives/xorg-devel/2010-March/006466.htmlSigned-off-by: Erik Boto
Signed-off-by: Mahesh Mahadevan
