14 Mar, 2014
1 commit
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MIPI CSI2 depends on this clock to work.
This patch also updates the binding document.Signed-off-by: Robby Cai
(cherry picked from commit 67e7963f6f7ddb6c001bb34c6af71f2330fd0e3f)
19 Feb, 2014
2 commits
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We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.[ To reduce the risk from code changing. This patch only takes care of pll4
related part. We might later need to add the relationship with pll5 too. ]Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 5b74b6b26e4b44d265090fc6ad15b15ccb7b5cff) -
This patch documents the Hannstar CABC driver's device tree bindings.
Signed-off-by: Liu Ying
(cherry picked from commit 0a6b9cf8548ffe03b8df494d08bece54ef3e528e)
07 Jan, 2014
1 commit
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Update for hsic controller
Signed-off-by: Peter Chen
03 Dec, 2013
1 commit
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The current mtd_type_show() misses the MTD_MLCNANDFLASH case.
This patch adds the case for it, and also updates the ABI.Signed-off-by: Huang Shijie
Signed-off-by: Brian Norris
20 Nov, 2013
3 commits
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Based on community patch-set, re-setup pcie driver on
imx6 platforms.
* re-fine the pcie clks.
* add the pcie support in dts files.Signed-off-by: Richard Zhu
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Add support for the PCIe port present on the i.MX6 family of controllers.
These use the Synopsis Designware core tied to their own PHY.Signed-off-by: Sean Cross
Signed-off-by: Shawn Guo
Signed-off-by: Bjorn Helgaas
Acked-by: Sascha Hauer
(cherry picked from commit bb38919ec56e0758c3ae56dfc091dcde1391353e) -
switch to community upstreamed pcie driver.
Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms"
This reverts commit d33370c77e57aed5a9b6733c9898418541fed54a.Conflicts:
Documentation/devicetree/bindings/clock/imx6q-clock.txt
arch/arm/mach-imx/clk-imx6q.cSigned-off-by: Richard Zhu
18 Nov, 2013
1 commit
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It is used to indicate whether we use SoC's usb charger
detection or not. Besides, we add anatop phandle since
we need to use anatop register to do most of charger detect operations.Signed-off-by: Peter Chen
14 Nov, 2013
1 commit
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In default way, we use the ecc_strength/ecc_step size calculated by ourselves
and use all the OOB area.This patch adds a new property : "fsl,use-minimum-ecc"
If we enable it, we will firstly try to use the datasheet's minimum required
ECC provided by the MTD layer (the ecc_strength_ds/ecc_step_ds fields
in the nand_chip{}). So we may have free space in the OOB area by using the
minimum ECC, and we may support JFFS2 with some SLC NANDs, such as Micron's
SLC NAND.If we fail to use the minimum ECC, we will use the legacy method to calculate
the ecc_strength and ecc_step size.Signed-off-by: Huang Shijie
Signed-off-by: Brian Norris
08 Nov, 2013
2 commits
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If wakeup is enabled, enter stop mode, else enter disabled mode.
Self wake can only work on stop mode.
For imx6q, the stop request has to be mannually assert on
IOMUX GPR13[28:29] register, we use syscon to control that bit.Signed-off-by: Dong Aisheng
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Add gpios for tranceiver control.
Before we have a common tranceiver binding, we use this way first.
Signed-off-by: Dong Aisheng
06 Nov, 2013
2 commits
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Add anatop phandle which is used to access anatop registers to
control PHY's power and other USB operations.Signed-off-by: Peter Chen
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Add "fsl,imx6q-usbphy" for imx6dq and imx6dl, add
"fsl,imx6sl-usbphy" for imx6sl.Signed-off-by: Peter Chen
05 Nov, 2013
3 commits
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We add a new sys node for ecc step size. So update the ABI document about it.
Signed-off-by: Huang Shijie
Signed-off-by: Artem Bityutskiy
[Brian: edited description, modified 'ecc_strength']
Signed-off-by: Brian NorrisSigned-off-by: David Woodhouse
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Now that the last user of NAND_BBT_SCANALLPAGES has been removed, let's
kill this peculiar BBT feature flag.Signed-off-by: Brian Norris
Reviewed-by: Ezequiel Garcia
Signed-off-by: Artem Bityutskiy
Signed-off-by: Huang Shijie -
NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its
single remaining user.NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway,
omap2 doesn't scan the chip for bad blocks (courtesy of
NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant.This patch drops the NAND_BBT_SCANEMPTY option.
[1] http://lists.infradead.org/pipermail/linux-mtd/2012-July/042902.html
Signed-off-by: Brian Norris
Cc: Ivan Djelic
Signed-off-by: Artem Bityutskiy
Signed-off-by: David Woodhouse
Signed-off-by: Huang Shijie
02 Nov, 2013
1 commit
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1. add epit1, epit2 and tzasc2 clock gate to clk tree so that
clk framework can manage these clock gates;2. adjust ipu2_di1 clock gate registry code to follow hardware
register CG index sequence.Signed-off-by: Anson Huang
30 Oct, 2013
22 commits
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Add caam clock gate nodes into clock tree, so that caam
driver can manage its clock gate to save power.Signed-off-by: Anson Huang
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This patch add MLB devicetree binding doc.
Signed-off-by: Luwei Zhou
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Help simplify the cleanup code for SPI master drivers by providing a
managed master registration function, ensuring that the master is
automatically unregistered whenever the device is unbound.Signed-off-by: Mark Brown
Signed-off-by: Huang Shijie -
spi: quad: fix the name of DT property in patch
The previous property name spi-tx-nbits and spi-rx-nbits looks not
human-readable. To make it consistent with other devices, using property
name spi-tx-bus-width and spi-rx-bus-width instead of the previous one
specify the number of data wires that spi controller will work in.
Add the specification in spi-bus.txt.Signed-off-by: wangyuhang
Signed-off-by: Mark Brown
Signed-off-by: Huang Shijie -
The DLL(Delay Line) is newly added to assist in sampling read data.
The DLL provides the ability to programmatically select a quantized
delay (in fractions of the clock period) regardless of on-chip variations
such as process, voltage and temperature (PVT).This patch adds a user interface to set slave delay line via device tree.
It's usually used in high speed mode like mmc DDR mode when the signal
quality is not good caused by board design, e.g. the signal path is too
long. User can manually set delay line to find a suitable data sampling
window for card to work properly.Signed-off-by: Dong Aisheng
Acked-by: Shawn Guo
Signed-off-by: Chris Ball -
-Copied Documentation from 3.5.7 Kernel
-Updated pinctrl node names.
-Corrected vendor fields in compatible fieldsSigned-off-by: Oliver Brown
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Added documentation for MIPI CSI2.
Signed-off-by: Oliver Brown
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Add ov5640 camera support on imx6sl-evk
Add binding document for csi/csi-v4l2-capture/ov5640Signed-off-by: Robby Cai
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There're two GPIOs connected to the headphone jack and microphone jack,
thus add the states detection.Reviewed-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
There's a missing script for hdmi audio support in current sdma driver,
thus add it.This HDMI script doesn't use bd to copy memory like a normal one does
but only to update the memory address for HDMI internal AHB DMA and
then trigger its procedure automatically.Signed-off-by: Nicolin Chen
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It's ported from 3.5.7 kernel. To test this driver, the EBook Daughter
Board need to be attached (on imx6dl sabresd or imx6sl evk board).Signed-off-by: Robby Cai
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merge the mach/epdc.h into linux/mxcfb_epdc.h
drop VM_RESERVED flag as deprecated.
drop VM_IO flag as it's automatically set in remap_pfn_range()
use instead of
use module_platform_driver()
add binding dts document for epdc fb driver
change the devname for interrupt from 'fb_dma' to 'epdc' to make it clearSigned-off-by: Robby Cai
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It's ported from v3.5.7 kernel, which contains a sensor driver
and regulator driver. It's used for E-Ink panel.add a parameter for mfd_add_devices() due to the propotype change.
use IS_ERR() to check the return value for devm_regulator_get().Signed-off-by: Robby Cai
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This patch implements a device-tree-only machine driver for Freescale
i.MX series Soc. It works with spdif_transmitter/spdif_receiver and
fsl_spdif.c drivers.Signed-off-by: Nicolin Chen
Acked-by: Stephen Warren
Signed-off-by: Mark Brown -
Add si476x machine dirver for i.MX series SoC and binding doc.
Signed-off-by: Nicolin Chen
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Add PCIe related clocks definitions and select pci on imx6
platformstoggle bit18 of grp1 fix pcie pm issue:
Set bit18 of gpr1 before enter into supend, and clean it
after resume, can fix the following errata.
Errata ERR005723_PCIe PCIe does not support L2 Power Down.Signed-off-by: Richard Zhu
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Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.Signed-off-by: Jingoo Han
Signed-off-by: Bjorn Helgaas
Cc: Pratyush Anand
Cc: Mohit KUMAR -
Exynos5440 has a PCIe controller which can be used as Root Complex.
This driver supports a PCIe controller as Root Complex mode.Signed-off-by: Surendranath Gurivireddy Balla
Signed-off-by: Siva Reddy Kallam
Signed-off-by: Jingoo Han
Acked-by: Bjorn Helgaas
Acked-by: Kukjin Kim
Cc: Pratyush Anand
Cc: Mohit KUMAR
Signed-off-by: Arnd Bergmann -
We allow the pci-mvebu driver to be compiled on the Kirkwood platform,
and add the 'marvell,kirkwood-pcie' as a compatible string supported
by the driver.Signed-off-by: Thomas Petazzoni
Tested-by: Andrew Lunn
Signed-off-by: Jason Cooper -
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.Signed-off-by: Thomas Petazzoni
Acked-by: Bjorn Helgaas
Signed-off-by: Jason Cooper -
re-use the upstreaming mxsfb.c code.
- add the lcdif axi clock for register and dram access
- set the lcdif pix's parent as pll5_video to get most accurate pix clock
- add binding doc for lcdif dtsSigned-off-by: Robby Cai
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This patch implements a device-tree-only CPU DAI driver for Freescale
S/PDIF controller that supports stereo playback and record feature.Signed-off-by: Nicolin Chen
Acked-by: Stephen Warren
Signed-off-by: Mark Brown
