03 Apr, 2014
1 commit
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CAAM depends on the clock used by WEIM interface. This patch supplied by
Haung Shijie corrects the issue by adding the clock to the device tree
entry for CAAM.Signed-off-by: Dan Douglass
02 Apr, 2014
7 commits
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Commit 14318efb(ARM: 7587/1: implement optimized percpu variable access)
introduces arm's __my_cpu_offset to optimize percpu vaiable access,
which really works well on hackbench, but will cause __my_cpu_offset
to return garbage value before it is initialized in cpu_init() called
by setup_arch, so accessing percpu variable before setup_arch may cause
kernel hang. But generic __my_cpu_offset always returns zero before
percpu area is brought up, and won't hang kernel.So the patch tries to clear __my_cpu_offset on boot CPU early
to avoid boot hang.At least now percpu variable is accessed by lockdep before
setup_arch(), and enabling CONFIG_LOCK_STAT or CONFIG_DEBUG_LOCKDEP
can trigger kernel hang.Signed-off-by: Ming Lei
Signed-off-by: Russell King
(cherry picked from commit 9394c1c65e61eb6f4c1c99f342b49e451ec337b6) -
commit afa31d8eb86fc2f25083e675d57ac8173a98f999 upstream.
The res variable is written before we've finished with the input
operands (namely the lock address), so ensure that we mark it as `early
clobber' to avoid unintended register sharing.Signed-off-by: Will Deacon
Signed-off-by: Russell King
Cc: Wang Weidong
Signed-off-by: Greg Kroah-Hartman -
commit 00efaa0250939dc148e2d3104fb3c18395d24a2d upstream.
Commit 15e7e5c1ebf5 ("ARM: 7749/1: spinlock: retry trylock operation if
strex fails on free lock") modifying our arch_spin_trylock to retry the
acquisition if the lock appeared uncontended, but the strex failed.This patch does the same for rwlocks, which were missed by the original
patch.Signed-off-by: Will Deacon
Signed-off-by: Russell King
Cc: Li Zefan
Signed-off-by: Greg Kroah-Hartman -
commit 15e7e5c1ebf556cd620c9b091e121091ac760f6d upstream.
An exclusive store instruction may fail for reasons other than lock
contention (e.g. a cache eviction during the critical section) so, in
line with other architectures using similar exclusive instructions
(alpha, mips, powerpc), retry the trylock operation if the lock appears
to be free but the strex reported failure.Reported-by: Tony Thompson
Signed-off-by: Will Deacon
Signed-off-by: Russell King
Cc: Li Zefan
Signed-off-by: Greg Kroah-Hartman -
commit 39544ac9df20f73e49fc6b9ac19ff533388c82c0 upstream.
Add DSB after icache flush to complete the cache maintenance operation.
Signed-off-by: Vinayak Kale
Acked-by: Catalin Marinas
Signed-off-by: Russell King
Signed-off-by: Greg Kroah-Hartman -
commit bae0ca2bc550d1ec6a118fb8f2696f18c4da3d8e upstream.
During __v{6,7}_setup, we invalidate the TLBs since we are about to
enable the MMU on return to head.S. Unfortunately, without a subsequent
dsb instruction, the invalidation is not guaranteed to have completed by
the time we write to the sctlr, potentially exposing us to junk/stale
translations cached in the TLB.This patch reworks the init functions so that the dsb used to ensure
completion of cache/predictor maintenance is also used to ensure
completion of the TLB invalidation.Reported-by: Albin Tonnerre
Signed-off-by: Will Deacon
Signed-off-by: Russell King
Signed-off-by: Greg Kroah-Hartman -
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.Signed-off-by: Ranjani Vaidyanathan
Signed-off-by: Fabio Estevam
01 Apr, 2014
1 commit
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These are Category B, hence workaround is essential.
Signed-off-by: Nitin Garg
17 Mar, 2014
2 commits
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As the sabreauto CPU board schematics mentions, the MIPI connector
isn't mechanically compatible with Freescale MIPI display and camera
board, then we have no way to support MIPI features currently on
this platform. So, let's disable MIPI CSI.Signed-off-by: Liu Ying
(cherry picked from commit 453d409281228429270b9f294728e5cad1c63ee0) -
As the sabreauto CPU board schematics mentions, the MIPI connector
isn't mechanically compatible with Freescale MIPI display and camera
board, then we have only the parallel CSI video input that is supported
by the v4l2_cap_0 node. So, let's remove the orphan one - v4l2_cap_1.Signed-off-by: Liu Ying
(cherry picked from commit 1396bc28eac7e968e278a9ce36cdc7a44b0417bd)
14 Mar, 2014
1 commit
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MIPI CSI2 depends on this clock to work.
This patch also updates the binding document.Signed-off-by: Robby Cai
(cherry picked from commit 67e7963f6f7ddb6c001bb34c6af71f2330fd0e3f)
06 Mar, 2014
2 commits
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.This patch ensures that the low power idle code checks the status of the
dummy ldo2p5 regulator before disabling LDO2p5.Signed-off-by: Ranjani Vaidyanathan
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
This patch adds the dummy regulator to the dts files.Signed-off-by: Ranjani Vaidyanathan
21 Feb, 2014
1 commit
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Add hwrng support for i.MX6SL.
1. Add RNG driver. This driver originated as fsl-rngc.c. It
has been modified to support device tree. The name has been
changed since it supports both b and c variants of RNG.
2. Added clock and compatible info to the device tree data.
3. Added the entry in the options in the Kconfig for hwrng.Signed-off-by: Dan Douglass
19 Feb, 2014
9 commits
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This patch mainly adds the clock route from external 24.576MHz OSC to internal
ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an
entirely synchronous clock source against CS42888.[ 1, We found if using pll4 to generate a 24.576MHz from inernal 24.0MHz OSC,
we would get noise during the audio playback via ESAI->CS42888 even though
this generated clock's rate is equal to the external one statistically. It
might be resulted from the tiny difference between two clock source, which
might be crucial to the sensitive CODEC we use -- CS42888. So we here apply
the old 3.0.35 way to feed ESAI the same clock source as CS42888.2, Ideally, we should use bypass mode for pll4 since we only need to get
the raw rate (24.576MHz) while currently bypass mode in clk-pllv3.c isn't
entirely supported: The clock rate would be fixed to 24.0MHz if setting to
bypass, which would cause child clock get an incorrect rate and the driver
who uses the child clock fail to derive a needed clock rate, and it might
be dangerous to involve the clk-pllv3.c driver to this fix. Thus we here
apply 3.0.35 way provisionally. ]Expected result:
anaclk2 0 1 24576000
lvds2_in 0 1 24576000
pll4_sel 0 1 24576000
pll4_audio 0 1 786432000
pll4_post_div 0 1 786432000
pll4_audio_div 0 1 786432000
esai_sel 0 1 786432000
esai_pred 0 1 98304000
esai_podf 0 1 24576000
esai 0 1 24576000Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 49584be724d4d9c7a753d2b981b3932d8d871eb4) -
We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.[ To reduce the risk from code changing. This patch only takes care of pll4
related part. We might later need to add the relationship with pll5 too. ]Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 5b74b6b26e4b44d265090fc6ad15b15ccb7b5cff) -
This patch removes the function imx6q_lvds_cabc_init() from the
machine layer since we have a dedicated Hannstar CABC driver to
control the CABC feature.Signed-off-by: Liu Ying
(cherry picked from commit b0d2154a9c63b2beba774e46b90ec3d55609c672) -
This patch removes the device tree node lvds_cabc_ctrl, since
it is replaced by hannstar_cabc_lvds0 and hannstar_cabc_lvds1.Signed-off-by: Liu Ying
(cherry picked from commit 6a3d2c5e858afeef695bcd9fe2ecc0933d3d29da) -
This patch adds a device tree node for the Hannstar CABC function.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.Signed-off-by: Liu Ying
(cherry picked from commit 0c98df5d1b04ea043e5279628aebf406c250f5e3) -
This patch adds a device tree node for the Hannstar CABC function.
The LVDS0 and LVDS1 interfaces of the i.MX6dql Sabreauto platform
shares a control pin for the CABC function, but LVDS1's control
wire is invalid for the unpopulated resistor R265 on the main board.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.Signed-off-by: Liu Ying
(cherry picked from commit 6af4f4ac7c361a60fe05400497f644db3adcfc94) -
This patch enables the Hannstar CABC driver in imx_v7_defconfig.
Signed-off-by: Liu Ying
(cherry picked from commit 9eeaeb6a259af6864a6db563100a300ba67ed83e) -
The bottom 16KB of the IRAM is reserved for the IRAM page table.
Reduce the available IRAM size for the other drivers by 16KB.Signed-off-by: Ranjani Vaidyanathan
-
Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the IRAM page table.
We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible.Signed-off-by: Ranjani Vaidyanathan
26 Jan, 2014
2 commits
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The ECSPI1 needs the GPIO3_19 to select/de-select the SPI NOR chip.
This patch adds a new pinctrl for this GPIO, and select this pinctrl
when we enable the ECSPI1.Signed-off-by: Huang Shijie
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The ECSPI needs the pin EIM_D18 which is controlled by the steering.
So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW
status.Signed-off-by: Huang Shijie
24 Jan, 2014
2 commits
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The CPU_DYING notifier is called by cpu stopper task which
does not own the context held in the VFP hardware. Calling
vfp_force_reload() has no effect.
Replace it with clearing vfp_current_hw_state.Signed-off-by: Yuanyuan Zhong
Signed-off-by: Russell King
(cherry picked from commit 384b38b66947b06999b3e39a596d4f2fb94f77e4) -
The WEIN NOR needs the pin EIM_D18 which is controlled by the steering.
So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW
status.Signed-off-by: Huang Shijie
23 Jan, 2014
1 commit
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Select HIGHMEM config to avoid the vmalloc region overlap on
boards that have big RAM.Previous imx_v7_defconfig change(CONFIG_CRYPTO_TEST) did NOT follow
the savedefconfig rule, fix it as well.Signed-off-by: Anson Huang
21 Jan, 2014
1 commit
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Add property "retain-state-suspended" in dts.
Signed-off-by: Robin Gong
(cherry picked from commit 7fa74454e8fb857b050901097bf78167ac3c04cd)
20 Jan, 2014
1 commit
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From schematic, below GPIO keys' active state is low, so we need
to set correct active state in dts.i.MX6Q/DL-SABRESD board: power, vol+ and vol-.
i.MX6Q/DL-SABREAUTO board: home, back, prog, vol+ and vol-.Signed-off-by: Anson Huang
19 Jan, 2014
1 commit
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The tcrypt module is used to test the crypto API by being passed a
mode= during module load. The test runs to completion before
insmod/modprobe returns. That makes the RCU stall detection in newer
kernels unhappy.The simple fix is to add CONFIG_PREEMPT to the kernel config. That's
what this patch does. If that introduces other problems,
crypto/tcrypt.c can be modified to call schedule() in the correct
places. Here's a patch that should work if this one has to be
reverted:diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 66d254c..b771f7d 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include "tcrypt.h"
#include "internal.h"@@ -182,6 +183,7 @@ static void test_cipher_speed(const char *algo, int enc, unsigned int sec,
goto out;
}+ schedule();
printk("test %u (%d bit key, %d byte blocks): ", i,
*keysize * 8, *b_size);@@ -448,6 +450,7 @@ static void test_hash_speed(const char *algo, unsigned int sec,
if (speed[i].klen)
crypto_hash_setkey(tfm, tvmem[0], speed[i].klen);+ schedule();
printk(KERN_INFO "test%3u "
"(%5u byte blocks,%5u bytes per update,%4u updates): ",
i, speed[i].blen, speed[i].plen, speed[i].blen / speed[i].plen);
@@ -688,12 +691,12 @@ static void test_ahash_speed(const char *algo, unsigned int sec,
break;
}+ schedule();
pr_info("test%3u "
"(%5u byte blocks,%5u bytes per update,%4u updates): ",
i, speed[i].blen, speed[i].plen, speed[i].blen / speed[i].plen);ahash_request_set_crypt(req, sg, output, speed[i].plen);
-
if (sec)
ret = test_ahash_jiffies(req, speed[i].blen,
speed[i].plen, output, sec);
@@ -853,6 +856,7 @@ static void test_acipher_speed(const char *algo, int enc, unsigned int sec,
goto out_free_req;
}+ schedule();
pr_info("test %u (%d bit key, %d byte blocks): ", i,
*keysize * 8, *b_size);@@ -934,6 +938,7 @@ static void test_available(void)
printk("alg %s ", *name);
printk(crypto_has_alg(*name, 0, 0) ?
"found\n" : "not found\n");
+ schedule();
name++;
}
}Signed-off-by: Jay Monkman
(cherry picked from commit 2dc1e6a900df2b575914a7c58fc08e4b072c0e67)
17 Jan, 2014
1 commit
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In order to support the dual video use-case, the current CMA reserved size is
not enough now, need enlarge the CMA size from 256M to 320M by default.Signed-off-by: Jason Liu
15 Jan, 2014
3 commits
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Enable the sdio wakeup capability for SDIO cards.
Note: we do not enable it for sabresd usdhc4 since it has a solid
eMMC card on it.Signed-off-by: Dong Aisheng
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All i.MX6 SabreAuto/SabreSD/EVK has the ability to keep card power
during suspend. So add this capability for them.Signed-off-by: Dong Aisheng
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SD3.0 cards require power cycle the card during suspend/resume,
or the card re-enumeration after resume will fail to be identified
as UHS card since the card is already working on 1.8v mode and refuse
to ack the S18R request, thus, it will then work on normal high speed
mode instead.We have to use external vmmc regulator to power cycle the card during
suspend/resume to reset card signal voltage to 3.3v frist for the later
1.8v voltage switch.However, due to the sabreauto board limitation, we can not use external
regulator to powere off card by default since the card power is shared
with card detect pullup. Disabling the vmmc regulator will also shutdown
the cd pullup which causes incorrect illusion of card exist.
(e.g. plug out the card, mmc core wll think the card is exist since cd pin
is low but it never can find the card)
HW rework removing R695 and enable PAD internal pullup is needed to
fix this isssue.User can manually open the mask of vmmc in dts to enable using external
regulator if your board has done the rework as said above.
Or by default we still do not power off card during suspend.Signed-off-by: Dong Aisheng
10 Jan, 2014
1 commit
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Currently, by default, we assign ipu display ports for the following
5 types of display devices on the imx6q sabresd platform in this way:
----------------------------------------
| | ipu | di |
|----------------------------------------|
| ldb channel0 | 1(0 for imx6dl) | 0 |
|----------------------------------------|
| ldb channel1 | 1(0 for imx6dl) | 1 |
|----------------------------------------|
| hdmi | 0 | 0 |
|----------------------------------------|
| mipi dsi | 0 | 0 |
|----------------------------------------|
| parallel output | 0 | 0 |
----------------------------------------So, the ipu0 di1 display port is not used by any display device.
This patch assigns this unused display port to mipi dsi by default.Acked-by: Robby Cai
Cc: Oliver Brown
Cc: Sandor Yu
Signed-off-by: Liu Ying
08 Jan, 2014
1 commit
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Enable viim device node in dts and enable in defconfig
Signed-off-by: Robin Gong
07 Jan, 2014
2 commits
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It is needed for USB HSIC controller
Signed-off-by: Peter Chen
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Since hsic has pin conflict with ethernet, we disable ethernet
at this dts. Besides, please make sure the line of data and strobe
has unchanged between board boots up and hsic controller has
benn enabled.Signed-off-by: Peter Chen
