18 Jul, 2014

2 commits

  • Move wl_surface_commit to work thread.
    Fix memory leak in wl_egl_window_resize.

    Date: Jul 10, 2014
    Signed-off-by Yong Gan
    Acked-by: Jason Liu
    (cherry picked from commit c114ec8a4c74fc2a2d0f64c60031c66d2225ff83)

    Loren Huang
     
  • Vivante patch name:
    fix_fsl_2d_base_on_p13.v2.rls.diff

    -Updated the outstanding request limit to 12.
    -Refined the 2D chip feature check.
    -Refine the 2D cache flush operation
    (avoid FE and PE access memory through the same port).
    -Enable cache flush for filterblt.
    -Dynamic enabling SPLIT_RECT by checking chip feature(disable for us)
    -Use brush stretch blt for clear operation.
    -Enable SplitFilterBlit to workaround the 2d hang issue in filterblit case.
    -Refine 2d line operation.

    Date: May 05, 2014
    Signed-off-by: Loren Huang
    Acked-by: Shawn Guo
    (cherry picked from commit 479b9125caefc45451aa1c4a1b7f2704b57831fa)

    Loren Huang
     

04 Apr, 2014

1 commit


03 Apr, 2014

3 commits


01 Apr, 2014

1 commit

  • This issue happens when multiple thread is trying to idle GPU at the
    same time, root cause is some wrong logic related with powerMutex which
    cause cpu still access GPU AHB register after GPU is suspend(clock off),
    that cause the bus lockup and make the whole system hang.

    Signed-off-by: Richard Liu
    Acked-by: Jason Liu
    (cherry picked from commit d48e52700c4177e94695cdbdb480cb38a88a5ddc)

    Richard Liu
     

27 Mar, 2014

3 commits


21 Mar, 2014

1 commit


18 Mar, 2014

3 commits


17 Mar, 2014

6 commits

  • The mipi csi2 code is ugly present in the capture pipeline setup/disable
    routions with '#ifdef CONFIG_MXC_MIPI_CSI2/#endif' protected. Whenever
    it finds mipi_csi2_info is not gotten correctly, it will return error to
    callers. This breaks the normally routines in which mipi csi2 is not used
    and mipi csi2 driver is disabled in its devicetree node(but with the
    Kconfig CONFIG_MXC_MIPI_CSI2 defined). A real example is the capture
    feature on the MX6 Sabreauto platforms. We have only parallel CSI input
    on it and the mipi csi2 driver is disabled in its devicetree node but with
    the Kconfig CONFIG_MXC_MIPI_CSI2 defined. So, a reasonable choice at present
    is not to return error if mipi_csi2_info cannot be gotten, though we could
    eventually re-organize the capture code for a better total solution in the
    future.

    Signed-off-by: Liu Ying
    (cherry picked from commit 8133b7fd26e8b068fa8ab9cd62eae090c76080be)

    Liu Ying
     
  • xserver will read default video mode in command line by sysfs node
    /sys/class/graphics/fb0/mode, but the sysfs node is not initialized
    when system bootup without hdmi cable plugin
    or frame buffer register in blank state.
    Fixed:
    - Remove unused previous_mode
    - Add default_mode, initialize in disp_init function.
    - Initialize fbi->mode in disp_init function and hdmi_setup function.

    Signed-off-by: Sandor Yu

    Sandor Yu
     
  • commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57 introduced an
    annoying kernel log by changing a pure debug info to error level.
    This patch reverts that change.

    Conflicts:

    drivers/media/video/mxc/capture/mxc_v4l2_capture.c

    Signed-off-by: Liu Ying
    (cherry picked from commit b635fadfdff01d0f6112956ac903d80c62fd648b)

    Liu Ying
     
  • commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57 added a hard
    coding for csi_parma.mclk setting to 27MHz. The comment added by
    that commit is totally wrong by telling that csi_param.mclk
    would be a kind of 'pixel clock' set in 'csi_data_dest' register.
    This patch removes the unnecessary mclk setting for csi_param.mclk
    variable, since it is only valid for CSI test mode.

    Conflicts:

    drivers/media/video/mxc/capture/mxc_v4l2_capture.c

    Signed-off-by: Liu Ying
    (cherry picked from commit bb5afd554c50b639f1e1b94481b24f35ae8c4dc5)

    Liu Ying
     
  • This patch removes test mode clock setting in function
    ipu_csi_init_interface(), since the setting is only
    necessary for function _ipu_csi_set_test_generator().
    This unnecessary setting is added wrongly by commit
    f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57.

    Signed-off-by: Liu Ying
    (cherry picked from commit 0f395a7aecfd2845df384c7a5a0045c86c3a2e20)

    Liu Ying
     
  • We reversed CCIR code1/2 setting before, which may brings
    captured frame quality issue(jaggy edge can be seen). This
    patch revert that change.

    Signed-off-by: Liu Ying
    (cherry picked from commit a4c2228f5428af02b9be87114d096340f9b58083)

    Liu Ying
     

14 Mar, 2014

1 commit

  • The following error was reported.

    -----------------------------------------------------------
    root@imx6qdlsolo:~# /unit_tests/mxc_v4l2_capture.out -d /dev/video1 1.yuv
    in_width = 176, in_height = 144
    out_width = 176, out_height = 144
    top = 0, left = 0
    mipi csi2 can not receive sensor clk!
    sensor chip is ov5640_mipi_camera
    sensor supported frame size:
    640x480
    320x240
    720x480
    720x576
    1280x720
    1920x1080
    2592x1944
    176x144
    1024x768
    sensor frame format: UYVY
    sensor frame format: UYVY
    sensor frame format: UYVY
    sensor frame format: UYVY
    sensor frame format: UYVY
    sensor frame format: UYVY
    sensor frame format: UYVY
    sensor frame format: UYVY
    sensor frame format: UYVY
    mipi csi2 can not receive sensor clk!
    mxc_v4l2_s_param: vidioc_int_s_parm returned an error -1
    VIDIOC_S_PARM failed
    get format failed

    -----------------------------------------------------------

    Root cause analysis:
    It only happens when HDMI is not used/enabled. There is a clock named
    video_27m which are needed by HDMI (as isfrclk's parent) and MIPI-CSI2 (as
    cfg_clk's parent). MIPI-CSI2 driver is lack of enabling this clock before
    start to work and only happen to work when HDMI driver enables this clock.

    Signed-off-by: Robby Cai
    (cherry picked from commit a6bbc7d56f261ab84e04071487264c6a519df758)

    Robby Cai
     

12 Mar, 2014

1 commit


07 Mar, 2014

1 commit


27 Feb, 2014

1 commit

  • When dma zone memory used up, gckOS_AllocateNonPagedMemory() will try to
    free non paged memory cache and allocate again. Such operation will cause
    twice memory mutex request and cause gpu driver hang.

    The solution is free the memory mutex at first before trying to free non
    paged memory cache.

    Date: Feb 27, 2014
    Signed-off-by: Loren Huang
    Acked-by: Shawn Guo
    (cherry picked from commit 79ed8edd23f990f6c1429154c2ee773c83bfd72e)

    Loren Huang
     

21 Feb, 2014

1 commit

  • Add hwrng support for i.MX6SL.

    1. Add RNG driver. This driver originated as fsl-rngc.c. It
    has been modified to support device tree. The name has been
    changed since it supports both b and c variants of RNG.
    2. Added clock and compatible info to the device tree data.
    3. Added the entry in the options in the Kconfig for hwrng.

    Signed-off-by: Dan Douglass

    Dan Douglass
     

20 Feb, 2014

2 commits

  • When split mode deinterlacing is the ipu_calc_stripes_sizes() was failing due
    to an unnecessary test. Added logic to use the maximal_stripe_width only if
    the flag parameter has the bit 0 clear for not equal stripe sizes.

    Signed-off-by: Oliver Brown

    Oliver Brown
     
  • For i.MX6 ARD board, the board not support read EDID from TV,
    so HDMI driver will create a default support mode list when system
    bootup.
    Because yocto xserver can not get video mode information from
    framebuffer now, and xserver will set default video mode XGA
    to framebuffer, but XGA mode is not support by hdmi.

    Remove XGA and SXGA from default support list.
    HDMI driver will find a nearest match video mode in support list.
    It is VGA mode. HDMI support VGA mode well.
    Issue is fixed.

    Signed-off-by: Sandor Yu

    Sandor Yu
     

19 Feb, 2014

1 commit

  • This patch adds Hannstar CABC driver support. The CABC
    function turns the backlight density of a display panel
    automatically according to the content shown on the panel.
    It is controlled(enabled/disabled) by a GPIO.

    Signed-off-by: Liu Ying
    (cherry picked from commit 2dddbc55bd8ae9461067e1a9d047b2994510e6d8)

    Liu Ying
     

13 Feb, 2014

2 commits

  • - add one imx pcie ep simple skeleton driver to demo
    the msi trigger capability in imx6 pcie rc/ep validation
    system
    - in order to avoid the modification of common codes,
    force the msi address to be 0x01ff8000

    Test howto:
    - Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images

    - EP side(console command and kernel message):
    root@sabresd_6dq:/ # memtool 0x1ff8000=0
    Writing 32-bit value 0x0 to address 0x01FF8000
    root@sabresd_6dq:/ #

    - RC side(console command and kernel message):
    root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
    384: 1 0 0 0 PCI-MSI

    - EP side(console command and kernel message):
    root@sabresd_6dq:/ # memtool 0x1ff8000=0
    Writing 32-bit value 0x0 to address 0x01FF8000

    - RC side(console command and kernel message):
    root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
    384: 2 0 0 0 PCI-MSI

    Signed-off-by: Richard Zhu

    Richard Zhu
     
  • - setup one new outbound memory region at rc side, used
    to let imx6 pcie rc can access the memory of imx6 pcie ep
    in imx6 pcie rc ep validation system.
    - set the default address of the ddr memory to be 0x4000_0000

    NOTE:
    - default address 0x4000_0000 of ep side would be
    accessed in this demo.
    Test howto:
    step1:
    EP side:
    1.1:
    echo 0x40000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/ep_bar0_addr

    1.2:
    memtool -32 0x40000000 4
    E
    Reading 0x4 count starting at address 0x40000000

    0x40000000: 6FE9E9F6 7583FBB9 39EAEFEA FBDCFD78

    step2:
    RC side:
    memtool -32 0x01000000=58D454DA
    memtool -32 0x01000004=7332095B

    step3:
    EP side:
    memtool -32 0x40000000 4
    E
    Reading 0x4 count starting at address 0x40000000

    0x40000000: 58D454DA 7332095B 39EAEFEA FBDCFD78

    Signed-off-by: Richard Zhu

    Richard Zhu
     

24 Jan, 2014

1 commit


23 Jan, 2014

2 commits

  • - add sata phy cr(offset:0x7f3f) reset in sata resume to
    workaround imx6q sata kinds of suspend resume link
    issues.
    - add sata phy cr reset during imx6q sata initialization,
    to initialize the sata phy to be an initialized state.
    - add about 100us delay between mpll_clk enable and cr-rst,
    make sure that the mpll_clk is stable.
    - add about 100us delay between cr-rst and waiting for rx_pll
    stable too, make sure that the cr-rst is finished.
    - change the tx level setting from 1.025v to be the default
    value 1.104v
    - make sure the sata phy internal pll ref clk enable is
    cleared before it is set, otherwise, the sata phy link
    maybe failed when some devices are used.

    Signed-off-by: Richard Zhu

    Richard Zhu
     
  • When device boot into console, frame buffer failed to work after
    suspend/resume.
    That is caused by LCDIF IP lost all registers configuration
    in suspend mode, and console didn't reconfiguration fb after resume.
    Same issue didn't found with Yocto UI.
    Reinitialize frame buffer driver after resume to fix the issue.

    Signed-off-by: Sandor Yu

    Sandor Yu
     

21 Jan, 2014

3 commits

  • Kernel will dump when run deinterlace stress test.
    It is caused by vditmpbuf being reallocated by another thread
    when one thread accesses it.
    Issue is fixed by putting these code in mutex.

    Kernel dump log:
    [Playing ][Vol=01][00:00:10/00:00:30][fps:32]Unable to handle kernel
    paging request at virtual address 607d6085
    pgd = 80004000
    [607d6085] *pgd=00000000
    Internal error: Oops: 5 [#1] SMP ARM
    Modules linked in:
    CPU: 0 PID: 50 Comm: ipu2_task Not tainted 3.10.17-02308-g3700819 #28
    task: ac1dc700 ti: ac1ba000 task.ti: ac1ba000
    PC is at __kmalloc+0x40/0x114
    LR is at __kmalloc+0x14/0x114
    pc : [] lr : [] psr: 200f0013
    sp : ac1bbbc8 ip : 008cc000 fp : 00001e40
    r10: ac772e00 r9 : 0057b255 r8 : 000000d0
    r7 : 00000790 r6 : ac773800 r5 : 607d6085 r4 : ac001b00
    r3 : 00000000 r2 : 814f92a0 r1 : 000000d0 r0 : 000398c9
    Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
    Control: 10c53c7d Table: 3c4c004a DAC: 00000015
    Process ipu2_task (pid: 50, stack limit = 0xac1ba238)
    Stack: (0xac1bbbc8 to 0xac1bc000)

    Signed-off-by: Sandor Yu

    Sandor Yu
     
  • __va function only can handle frame buffer from low memory.
    Use page_address function to replace it, that can handle
    frame buffer from both lower and high memory.

    Use ioremap_nocache function to handle Frame buffer
    from GPU reserve memory pool.

    Correct vdi data save buffer size, save both luma and chroma part for
    interleaved YUV format.
    For non-interleaved and partial-interleaved YUV format,
    save luma part data, chroma part is not covered in the patch.

    Signed-off-by: Sandor Yu

    Sandor Yu
     
  • gpio-leds driver common framework didn't take care of this case if use CONFIG_OF
    , add property "retain-state-suspended" in dts and check it while gpio-leds
    device created.

    Signed-off-by: Robin Gong
    (cherry picked from commit 118c650de0bb518d377b0e6427b38fc101fe31aa)

    Robin Gong
     

20 Jan, 2014

1 commit


17 Jan, 2014

1 commit

  • The usdhc of i.MX6Q/DL can work well under low power mode without
    request high bus freq. So we do not need request bus freq for i.MX6Q/DL.
    It can save power for i.MX6D/DL due to it saves a lot busfreq switch
    cost as well as the CPU time runing on high bus freq after switch
    during low power mode.

    A new flag ESDHC_FLAG_BUSFREQ is added to indicated this requirement.
    Currently only i.MX6SL is using it.

    Signed-off-by: Dong Aisheng
    (cherry picked from commit 075196777d00bf9507d68a76bf25f6c7e776102f)

    Dong Aisheng
     

16 Jan, 2014

2 commits