16 Jan, 2014
1 commit
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Some SoCs can only work in mono or stereo mode at one time. So if
we let them capture a mono stream while playing a stereo stream,
there might be a problem occur to one of these two streams: double
paced or slowed down.In soc-pcm.c, we have soc_pcm_apply_symmetry() to apply the rate
symmetry. But we don't have one for channels.Likewise, we can treat symmetric_rate as a solution for those SoCs
or CODECs which can not handle asymmetrical LRCLK. But it's also
impossible for them to handle asymmetrical BCLK. And accodring to
BCLK = LRCLK * channel number * slot size(fixed or sample bits),
sample bits might also be a problem if they are not using a fixed
slot size.Thus, this patch applys symmetry for channels and sample bits.
Meanwhile, there might be a race between two substreams if starting
simultaneously. Previously, we only added warning to compalin but
still using conservative way to let it carry on. However, this patch
rejects the second stream with any unmatched parameter to make sure
the first existing stream won't be broken.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 3635bf09a89cf92b80ac44198c5c8f0989624ea6)
(cherry picked from commit bb3317659966b170d9481fad887df8808774c696)
07 Jan, 2014
2 commits
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The glue layer may need to know current available role, add
ci_hdrc_query_available_role for that.Signed-off-by: Peter Chen
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Add imx6 HSIC support
Signed-off-by: Peter Chen
06 Jan, 2014
1 commit
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This change add support for new dma buffer type(writecombine and cacheable)
which allows user application has more choices for the buffer type. And if
the dma buffer is cacheable, then add flush interfaces to make it cache
coherent when necessary.Signed-off-by: Fancy Fang
02 Jan, 2014
2 commits
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Change irq_pending field in struct pxp_irq_info to a atomic
type. So the spin lock in pxp_irq_info is unnecessary.Signed-off-by: Fancy Fang
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The allocated DMA channels via some opened file descriptor is better
to be bound to this descriptor. Since this can avoid some application
to fake a channel id which may be requested by other applications to
request PXP service. And also, this make it easier to release the dma
channel when application exists abnormally or forgets to release it
explicitly.Signed-off-by: Fancy Fang
26 Dec, 2013
1 commit
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The cpu_addr field in struct pxp_mem_desc cannot be used
by user application, so it is not necessary to pass this
field data to user. Now the similar field 'virtual' in
struct pxp_buf_obj is used to store the kernel space
virtual addr for allocated dma buffer.Signed-off-by: Fancy Fang
25 Dec, 2013
2 commits
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Create pxp_info struct data for each opened device file descriptor.
And bind all the allocated dma buffers to this struct for each opened
file. This makes the dma buffer lists management safer, more effective
and more flexible.Signed-off-by: Fancy Fang
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Move two struct definitions defined in pxp_device.c to pxp_device.h.
Now the pxp_device.h has been created for PXP device driver. So all
the type definition should stay in header file not c source file.Signed-off-by: Fancy Fang
23 Dec, 2013
1 commit
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The original mipi csi2 driver uses readl()/writel()
to access the 32 bit mipi csi2 registers in the
following way where info->mipi_csi2_base is a pointer
which points to a 32 bit I/O memory cell of the mipi
csi2's base address:
writel(value, info->mipi_csi2_base + offset);
readl(info->mipi_csi2_base + offset);This makes the register offset values shrink 4 times,
comparing to the offset values documented in the
reference manual. For example, we need to change the
offset value from 0x004 to 0x001 so that we may access
the register MIPI_CSI2_N_LANES correctly.This patch redefines the type of info->mipi_csi2_base
to 'void __iomem *', then the offset values can be the
same to what they are documented. Also, the macro names
for the registers are aligned to the documentation.Acked-by: Robby Cai
Cc: Oliver Brown
Signed-off-by: Liu Ying
19 Dec, 2013
1 commit
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Some definitions used only by PXP device driver should not stay in
pxp_dma.h which is shared by PXP, EPDC and V4L2. So the patch creates
a new header file pxp_device.h to hold these definitions.Signed-off-by: Fancy Fang
17 Dec, 2013
1 commit
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Remove the __u32 macro definition in pxp_dma.h. But include
in pxp_dma.h to make sure user application
which include pxp_dma.h to be compiled with no error.Signed-off-by: Fancy Fang
13 Dec, 2013
4 commits
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struct pxp_irq_info is only used by PXP device driver, so it is unreasonable
to define it in pxp_dma.h which will be included by EPDC, V4L2 PXP and PXP
device driver.Signed-off-by: Fancy Fang
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This mutex lock is no longer necessary in PXP dma driver. After
the commit "ENGR00291400 PXP: Organize PXP task queue to be FIFO",
protection fields can be protected by the spin lock in PXP channel
now.Signed-off-by: Fancy Fang
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After the commit "ffcad666548417ef21937e0a755d85ab922313a9" pushed,
adding this support in PXP device driver is also necessary. This
change allows users to submit more than one PXP tasks followd by
only one wait for finished ioctl. It means that users can wait for
more than one tasks done by calling one PXP_IOC_WAIT4CMPLT ioctl.Signed-off-by: Fancy Fang
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The requested PXP tasks were handled based on channel unit. All the
tasks in one channel were handled one by one, and the tasks in another
channel only can get chance after all the tasks in previous channel
were finished. So this may allow some channel occupies PXP hardware
exclusively all the time, and other channels may never get PXP services.
So this change makes the PXP task queue to be a FIFO to avoid this kind
of unfair usage for PXP.Signed-off-by: Fancy Fang
06 Dec, 2013
1 commit
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In previous PXP driver, the number of tx descriptors allocated
for each channel is a constant 16 and they can only be allocated
during PXP initialization. But since the driver allows users to
queue more than one PXP tasks for each channel before issuing
pending tasks, so in this case the descriptors may be not enough
for some cases.Signed-off-by: Fancy Fang
03 Dec, 2013
1 commit
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The IPUv3 IDMAC has a bug to read 32bpp pixels from a
graphics plane whose alpha component is at the most
significant 8 bits. The bug only impacts on cases in which
the relevant separate alpha channel is enabled.
This patch adds check for the errata so that the bad
cases won't be triggered.Signed-off-by: Liu Ying
27 Nov, 2013
1 commit
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We are missing spba clock in imx6sl's clock tree, thus add it.
Acked-by: Wang Shengjiu
Acked-by: Shawn Guo
Signed-off-by: Nicolin Chen
22 Nov, 2013
1 commit
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The max timeout counter of some SoCs like i.MX6 uSDHC may not be standard,
add SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER quirk to get the correct max timeout
counter from platform specific code.
Then we can calculate the correct max_discard_to value.Signed-off-by: Dong Aisheng
20 Nov, 2013
9 commits
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Support YUV formats like: I420, NV12, NV21, UYVY,
YUYV, VYUY, YVYU, NV16, NV61 and YV12.
Support rotation in both stages before and after alpha blending.Signed-off-by: Fancy Fang
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This commit adds a very basic registry of msi_chip structures, so that
an IRQ controller driver can register an msi_chip, and a PCIe host
controller can find it, based on a 'struct device_node'.Signed-off-by: Thomas Petazzoni
Acked-by: Benjamin Herrenschmidt
Acked-by: Rob Herring
Signed-off-by: Jason Cooper -
This function can be used to parse a bus-range property as specified by
device nodes representing PCI bridges.Signed-off-by: Thierry Reding
Signed-off-by: Jason Cooper -
This function can be used to parse the device and function number from a
standard 5-cell PCI resource. PCI_SLOT() and PCI_FUNC() can be used on
the returned value obtain the device and function numbers respectively.Signed-off-by: Thierry Reding
Signed-off-by: Thomas Petazzoni
Signed-off-by: Jason Cooper -
The new struct msi_chip is used to associated an MSI controller with a
PCI bus. It is automatically handed down from the root to its children
during bus enumeration.This patch provides default (weak) implementations for the architecture-
specific MSI functions (arch_setup_msi_irq(), arch_teardown_msi_irq()
and arch_msi_check_device()) which check if a PCI device's bus has an
attached MSI chip and forward the call appropriately.Signed-off-by: Thierry Reding
Signed-off-by: Thomas Petazzoni
Acked-by: Bjorn Helgaas
Tested-by: Daniel Price
Tested-by: Thierry Reding
Signed-off-by: Jason Cooper -
Until now, the MSI architecture-specific functions could be overloaded
using a fairly complex set of #define and compile-time
conditionals. In order to prepare for the introduction of the msi_chip
infrastructure, it is desirable to switch all those functions to use
the 'weak' mechanism. This commit converts all the architectures that
were overidding those MSI functions to use the new strategy.Note that we keep two separate, non-weak, functions
default_teardown_msi_irqs() and default_restore_msi_irqs() for the
default behavior of the arch_teardown_msi_irqs() and
arch_restore_msi_irqs(), as the default behavior is needed by x86 PCI
code.Signed-off-by: Thomas Petazzoni
Acked-by: Bjorn Helgaas
Acked-by: Benjamin Herrenschmidt
Tested-by: Daniel Price
Tested-by: Thierry Reding
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Martin Schwidefsky
Cc: Heiko Carstens
Cc: linux390@de.ibm.com
Cc: linux-s390@vger.kernel.org
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: H. Peter Anvin
Cc: x86@kernel.org
Cc: Russell King
Cc: Tony Luck
Cc: Fenghua Yu
Cc: linux-ia64@vger.kernel.org
Cc: Ralf Baechle
Cc: linux-mips@linux-mips.org
Cc: David S. Miller
Cc: sparclinux@vger.kernel.org
Cc: Chris Metcalf
Signed-off-by: Jason Cooper -
Because of the encoding of the "Multiple Message Capable" and "Multiple
Message Enable" fields, a device can only advertise that it's capable of a
power-of-two number of vectors, and the OS can only enable a power-of-two
number.For example, a device that's limited internally to using 18 vectors would
have to advertise that it's capable of 32. The 14 extra vectors consume
vector numbers and IRQ descriptors even though the device can't actually
use them.This fix introduces a 'msi_desc::nvec_used' field to address this issue.
When non-zero, it is the actual number of MSIs the device will send, as
requested by the device driver. This value should be used by architectures
to set up and tear down only as many interrupt resources as the device will
actually use.Note, although the existing 'msi_desc::multiple' field might seem
redundant, in fact it is not. The number of MSIs advertised need not be
the smallest power-of-two larger than the number of MSIs the device will
send. Thus, it is not always possible to derive the former from the
latter, so we need to keep them both to handle this case.[bhelgaas: changelog, rename to "nvec_used"]
Signed-off-by: Alexander Gordeev
Signed-off-by: Bjorn Helgaas -
PCIe requires additional bits be defined for GPR8 and GPR12.
Signed-off-by: Sean Cross
Signed-off-by: Shawn Guo
Signed-off-by: Bjorn Helgaas
(cherry picked from commit 8d6a35fb13406f87d926fffeee0d70360ce3077d) -
switch to community upstreamed pcie driver.
Revert "ENGR00275213-2 ARM: imx6q: update the pcie bits definitions of gpr"
This reverts commit 0ddad708c7484a8b5d2016d31fda2bd8b9b8f275.Signed-off-by: Richard Zhu
18 Nov, 2013
2 commits
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- Change .notify's return value from void to int.
- Add CI_HDRC_CONTROLLER_CHARGER_EVENT and
CI_HDRC_CONTROLLER_CHARGER_POST_EVENT to finish the USB charger
detection flow.
- Add usb_gadget_vbus_connect for only notify udc when vbus
is on, the main reason we add it is we don't want the first
notification when the vbus is off, it causes the
dev->power.usage_count equals -1 when do charger detection.Signed-off-by: Peter Chen
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Add imx6 USB charger detection, the vbus supplier will create and
remove struct usb_charger, and notify vbus connect and disconnect
event. The detail USB charger detection flow is at: "i.MX6 RM,
Chapter Universal Serial Bus 2.0 Integrated PHY (USB-PHY),
Charger detection, Charger detection software flow".Since imx6 only has charger detection function, and no charging
current function is existed. It the user wants the detection abilities
from SoC, it can use this detection method
(add imx6-usb-charger-detection at dts). If the charger IC
already has USB charger detection function, and the user wants
to use the detection method from charger IC, please do not add
imx6-usb-charger-detection property at dts.Signed-off-by: Peter Chen
12 Nov, 2013
1 commit
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This patch fixes the hang and crash issue of MLB SYNC mode in the driver.
The MITB will casue Sabreauto to hang and crash when testing the SYNC mode.
It is because MITB will cause something error on MLB bus when stopping the
SYNC test. The Sabreauto will keep entering error ISR and hang. Since we
don't know the details about MITB, we make drivers provide IO_CTRL
interface to disable the interrupt in SYNC mode.Signed-off-by: Luwei Zhou
08 Nov, 2013
3 commits
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Although the HC supports HS200 (eMMC) the caps2 are always zero; this
means there's no way to use the super speed mode (when init the card).If the HC support SDR104, for SD3.0, so it also supports HS200 for eMMC
and this patch just sets the MMC_CAP2_HS200 in the host caps2 field.Reported-by: Youssef Triki
Signed-off-by: Giuseppe Cavallaro
Reviewed-by: Philip Rakity
Signed-off-by: Chris Ball
(cherry picked from commit 156e14b126ffb6f040bc6f1aff3c51077e42a744) -
If card power is dependent on SD bus power then the host controller
must not be runtime suspended while the card is powered up. Add
the ability to stay runtime-resumed in that case and enable it with a new
quirk SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON.Signed-off-by: Adrian Hunter
Signed-off-by: Chris Ball
(cherry picked from commit f0710a557cb17746b09234f01073a2cdafe4f4a5) -
The ACMD23 unwork issue is fixed now. so the former quirk to disable
ACMD23 can be removed.This reverts commit fd27fce042bfd289eab6dbb7c98ab3adb48ca25b.
Signed-off-by: Dong Aisheng
06 Nov, 2013
5 commits
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When the port goes to suspend or finishes resme, it needs to
notify PHY, it is not a standard EHCI operation, so we add a
quirk for it.Signed-off-by: Peter Chen
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This commit adds runtime and system power management support for
chipidea core. The runtime pm support is controlled by glue
layer, it can be enabled by flag CI_HDRC_SUPPORTS_RUNTIME_PM.Signed-off-by: Peter Chen
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This API is used to set wakeup enable at PHY registers, in that
case, the PHY can be waken up from suspend due to external events,
like vbus change, dp/dm change and id change.Signed-off-by: Peter Chen
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They are used to notify PHY that the controller enters suspend
or finishes resume.Signed-off-by: Peter Chen
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According to Freescale imx28 Errata, "ENGR119653 USB: ARM to USB
register error issue", All USB register write operations must
use the ARM SWP instruction. So, we implement special hw_write
and hw_test_and_clear for imx28.Discussion for it at below:
http://marc.info/?l=linux-usb&m=137996395529294&w=2Signed-off-by: Peter Chen