12 Dec, 2014
1 commit
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This property is used to wakeup transceiver if it's in
sleep mode.Signed-off-by: Dong Aisheng
01 Dec, 2014
1 commit
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The new property "ddrsmp" was added into device tree. Update the doc
accordingly.Signed-off-by: Ye.Li
(cherry picked from commit 4239df12c5d6c3ac19a25e120ffe17df93c358a3)
28 Oct, 2014
4 commits
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Implement machine driver for mqs, which use the sai as cpu dai.
sai work on master mode.Signed-off-by: Shengjiu Wang
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Implement codec driver for mqs. mqs is a very simple IP. which support:
Word length: 16bit.
DAI format: Left-Justified, slave mode.Signed-off-by: Shengjiu Wang
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The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added
new Device Tree bindings for Asynchronous and Synchronous modes support.
However, these two shall not be present at the same time.So this patch just simply makes them exclusive so as to avoid incorrect
Device Tree binding usage.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit ce7344a4ebabe90e064d3e087727f45624cdc942) -
SAI supports these operation modes:
1) asynchronous mode
Both Tx and Rx are set to be asynchronous.
2) synchronous mode (Rx sync with Tx)
Tx is set to be asynchronous, Rx is set to be synchronous.
3) synchronous mode (Tx sync with Rx)
Rx is set to be asynchronous, Tx is set to be synchronous.
4) synchronous mode (Tx/Rx sync with another SAI's Tx)
5) synchronous mode (Tx/Rx sync with another SAI's Rx)* 4) and 5) are beyond this patch because they are related with another SAI.
As the initial version of this SAI driver, it supported 2) as default while
the others were totally missing.So this patch just adds supports for 1) and 3).
Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 08fdf65e37d560581233e06a659f73deeb3766f9)
20 Oct, 2014
2 commits
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Enable DMA support on i.mx6. The read speed can increase from 600KB/s
to 1.2MB/s on i.mx6q. You can disable or enable dma function in dts.
If not set "dma-names" in dts, spi will use PIO mode. This patch only
validate on i.mx6, not i.mx5, but encourage ones to apply this patch
on i.mx5 since they share the same IP.Note:
Sometime, there is a weid data in rxfifo after one full tx/rx
transfer finish by DMA on i.mx6dl, so we disable dma functhion on
i.mx6dl.Signed-off-by: Frank Li
Signed-off-by: Robin Gong
Acked-by: Marek Vasut
Signed-off-by: Mark Brown
(cherry picked from commit f62caccd12c17e4cb516d43a6e4dd8a3abc1f7e0) -
add optional property devicetree for SPI slave nodes
into devicetree so that LSB mode can be enabled by devicetree.Signed-off-by: Zhao Qiang
Signed-off-by: Mark Brown
(cherry picked from commit cd6339e6ced387ad67b5551dd2931cfd7e8b970b)
26 Sep, 2014
2 commits
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Adds chipidea to the list of DT vendor prefixes.
Signed-off-by: Peter Chen
Signed-off-by: Greg Kroah-HartmanConflicts:
Documentation/devicetree/bindings/vendor-prefixes.txt
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TPL (Targeted Peripheral List) is needed for targets host
(OTG and Embedded Hosts) for usb certification and other
vendor specific requirements.Signed-off-by: Peter Chen
Signed-off-by: Greg Kroah-Hartman
29 Aug, 2014
1 commit
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User can specify clocks in devicetree which is used for accessing the registers
in this regmap.Signed-off-by: Dong Aisheng
28 Aug, 2014
29 commits
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Since uart SDMA can work for Atheros BT module in android environment,
the previous patch (commit f337845718) disable SDMA mode in default,
now revert the patch to avoid the big change in dts for all platforms.By default, we enable SDMA mode for uart.
Signed-off-by: Fugang Duan
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Now uart cannot work well with CSR/Atheros BT module with SDMA
mode. Set it to cpu mode before SDMA mode work.To enable dma mode, just add "fsl,dma-mode" in the device tree for
the node.Signed-off-by: Fugang Duan
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Add dcic1 and dcic define in imx6q clock tree.
Signed-off-by: Sandor Yu
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The clk_set_parent() on the buggy mux ldb_di0_sel and ldb_di1_sel can
possibly lock up the downstream divider and result in no clock output.
Let's hard-code the parent to be pll2_pfd0_352m at boot time, and hide
these two buggy muxes from clk API. Then no clk_set_parent() can be
called on these muxes to switch parent clock at run-time.Kernel parameter 'ldb_di_clk_sel' is created to select parent of
ldb_di_clk among the following clocks at boot time.'pll5_video_div'
'pll2_pfd0_352m'
'pll2_pfd2_396m'
'mmdc_ch1_axi'
'pll3_usb_otg'Example format: ldb_di_clk_sel=pll5_video_div
If the kernel parameter is absent or invalid, pll2_pfd0_352m will be
selected by default.Signed-off-by: Shawn Guo
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The current imx6q clock driver combines two mux clocks axi_alt_sel and
axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a
glitchless one. Fix it to match the clock tree in Reference Manual,
and update busfreq driver regarding parent switching on that. Note,
the parent checking before calling clk_set_parent() in busfreq driver
isn't really necessary, because clk API will make the check and do
nothing if the new parent is the same one as the old.One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy axi_alt_sel only when axi_sel selects the other
path, i.e. periph. Otherwise, a glitch could be generated on
axi_alt_sel and get propagated into the divider axi_podf. In that case,
axi_podf gets locked up and axi clock has no output.Signed-off-by: Shawn Guo
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The patch adds the basic CAN TX/RX function support for Bosch M_CAN controller.
For TX, only one dedicated tx buffer is used for sending data.
For RX, RXFIFO 0 is used for receiving data to avoid overflow.
Rx FIFO 1 and Rx Buffers are not used currently, as well as Tx Event FIFO.Due to the message ram can be shared by multi m_can instances
and the fifo element is configurable which is SoC dependant,
the design is to parse the message ram related configuration data from device
tree rather than hardcode define it in driver which can make the message
ram using fully transparently to M_CAN controller driver,
then we can gain better driver maintainability and future features upgrade.M_CAN also supports CANFD protocol features like data payload up to 64 bytes
and bitrate switch at runtime, however, this patch still does not add the
support for these features.Signed-off-by: Dong Aisheng
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Add mega fast domain power off feature in DSM, it can save about
0.72mW power;If there is any module in Mega/Fast domain enabled as wakeup source,
then Mega/Fast domain's power will be kept on in DSM.Signed-off-by: Anson Huang
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commit 79d9701559a9f3e9b2021fbd292f5e70ad75f686 upstream.
The standard interrupts property in device tree can only handle
interrupts coming from a single interrupt parent. If a device is wired
to multiple interrupt controllers, then it needs to be attached to a
node with an interrupt-map property to demux the interrupt specifiers
which is confusing. It would be a lot easier if there was a form of the
interrupts property that allows for a separate interrupt phandle for
each interrupt specifier.This patch does exactly that by creating a new interrupts-extended
property which reuses the phandle+arguments pattern used by GPIOs and
other core bindings.Signed-off-by: Grant Likely
Acked-by: Tony Lindgren
Acked-by: Kumar Gala
[grant.likely: removed versatile platform hunks into separate patch]
Cc: Rob Herring
Signed-off-by: Shawn Guo -
The upsteamed commit is 0c516b4ff85c0be4cee5b30ae59c9565c7f91a00
ASoC: cs42xx8: Add codec driver support for CS42448/CS42888
This patch adds support for the Cirrus Logic CS42448/CS42888 Audio CODEC that
has six/four 24-bit AD and eight 24-bit DA converters.[ CS42448/CS42888 supports both I2C and SPI control ports. As initial patch,
this patch only adds the support for I2C. ]Signed-off-by: Nicolin Chen
Acked-by: Brian Austin
Acked-by: Paul Handrigan
Signed-off-by: Mark Brown
Signed-off-by: Shengjiu Wang -
cherry-picked commit is 43d24e76b69826ce32292f47060ad78cdd0197fa
Header of this commit is "ASoC: fsl_esai: Add ESAI CPU DAI driver", use upstream
driver to replace current one.Merged feature is:
1. Move setting of PRRC and PCRC to the end of hw_params, and disable it in
shutdown function.
2. Merged the xrun handler with this commit.
3. Use dma init with NO_RESIDUE|NO_DT|COMPAT.
4. Add spba clock for ESAISigned-off-by: Shengjiu Wang
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There are three clock for ESAI, esai_extal, esai_ipg, esai_mem.
Make the clock for ESAI more clear.Signed-off-by: Shengjiu Wang
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Change the output-rate, output-width to p2p-rate, p2p-width.
Signed-off-by: Shengjiu Wang
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The current imx-wm8962 machine driver is designed for SSI as CPU DAI only
while as its name we should make the driver more generic to any other CPU
DAI on i.MX serires -- ESAI, SAI for example.So this patch makes the driver more general so as to support those non-SSI
cases.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
The new Solo X has more requirements for SDMA events. So it creates a event mux
to remap most of event numbers in GPR (General Purpose Register). If we want to
use SDMA support for those module who do not get the even number as default, we
need to configure GPR first.Thus this patch adds this support of GPR event remapping configuration to the
SDMA driver.Acked-by: Robin Gong
Acked-by: Huang Shijie
Signed-off-by: Nicolin Chen -
The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.So this patch adds these clocks and their clock controls to the driver.
[ To concern the old DTB cases, I've added a bit of extra code to make
the driver compatible with them. And by marking clock NULL if failed
to get, the clk_prepare() or clk_get_rate() would easily return 0
so no further path should be broken. -- by Nicolin ]Signed-off-by: Nicolin Chen
Acked-by: Xiubo Li
Signed-off-by: Mark Brown
(cherry picked from commit 17d1eb6628e70488c44c46003dcfe583696bb7b7) -
Make use of the new enable_gpio field and allow it to be set from DT as
well. Now that all legacy users of platform data have been converted to
initialize this field to an invalid value, it is safe to use the field
from the driver.Signed-off-by: Thierry Reding
(cherry picked from commit 8265b2e4e62632b01f998095d1bbda4d281629fe) -
add snvs power key driver since ic team has fix some issues of SNVS on i.mx6sx
Signed-off-by: Robin Gong
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Signed-off-by: Denis Carikli
Signed-off-by: Dmitry Torokhov -
The next coming i.MX6 Solo X SoC also contains SAI module while we use
imp_pcm_init() for i.MX platform.So this patch adds one compatible route for imx6sx and updates the DT
doc accordingly.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 30c35252aadb460e009ca8a3fdc8891903bdfc66)[ Added essential parameters to imx_pcm_init() calling due to build error,
resulted from the define change of the function on the upstream. ]Signed-off-by: Nicolin Chen
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This adds the Document for Freescale SAI driver under
Documentation/devicetree/bindings/sound/.Signed-off-by: Xiubo Li
Signed-off-by: Mark Brown
(cherry picked from commit b6344859b911990152e5ee411e62b82eb968004f) -
This patch adds SAI script support to imx-sdma.
Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
The current imx-sgtl5000 driver always attaches the cpu-dai to ssi while
in fact it could be attached to other cpu-dais like SAI. Thus this patch
use a general code to support another cpu-dai. And meanwhile update the
devicetree for i.MX6 Series.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
Add fixed phy address support.
i.MX6sx has two MACs, and MAC1 mdio bus connects to two phys which
means MAC2 share MDIO bus with MAC1. So for any one of the two MACn,
which can scan two phy address. For current implementment, it selects
the little address for the default address and binding with the phy.
For the situation, user can add the fixed phy address to DTS.Signed-off-by: Fugang Duan
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We have already renamed the file name, change doc name at this
patch.Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Signed-off-by: Peter Chen
Signed-off-by: Greg Kroah-Hartman -
This patch makes it possible to set the chipidea udc into full-speed only mode.
It is set by the oftree property "maximum-speed = full-speed".Signed-off-by: Peter Chen
Signed-off-by: Michael Grzeschik
Signed-off-by: Marc Kleine-Budde
Signed-off-by: Greg Kroah-Hartman -
this helper will be used for controllers which
want to work at a lower speed even though they
support higher USB transfer rates.One such case is Texas Instruments' AM437x
SoC where it uses a USB3 controller without
a USB3 PHY, rendering the controller USB2-only.Signed-off-by: Felipe Balbi
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MIPI CSI2 depends on this clock to work.
This patch also updates the binding document.Signed-off-by: Robby Cai
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This patch adds mxc display driver support for the mxsfb
driver so that it may interactive with encoder drivers.Signed-off-by: Liu Ying
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This patch almost reworks the LDB driver to make the
implementation simpler and clearer. The new version
should support all the LDB modules embedded in imx53,
imx6qdl and imx6sx. The lvds-channel subsidiary DT
node is introduced to represent each LVDS channel.
People may specify a channel's CRTC, working mode(dual
mode or split mode), data width, data mapping, display
timing and if it is a primary channel in the node.Change logs:
* Use CTRC concept so that the driver may support both
IPU and LCDIF as the display engines.
* Add mxc dispdrv enable() callback.
* Cache LDB ctrl register value at probe()/setup()/
enable() stages and finally write to the register at
enable() stage.
* Simplify logics for setting ctrl/bus muxing/clocks.
* Use regmap to write crtl and bus muxing registers.
* Remove LDB description in DT binding doc fsl_ipuv3_fb.txt.
Instead, add a new one in fsl,ldb.txt.Signed-off-by: Liu Ying
