04 Jan, 2015
1 commit
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This reverts commit 178bb7bed5b467463a3861aecdd5361ea9d295b7.
It causes the USB audio which defines quirk will be dead lock at its resume code
Signed-off-by: Peter Chen
19 Dec, 2014
1 commit
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Implement reset_resume callback so that the mixer values are properly
restored. Still no boot quirks are called, so it might not work well
on some devices.Signed-off-by: Takashi Iwai
17 Dec, 2014
2 commits
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The default setting of sai is RX sync with TX, TX output the I2S clock. So
When recording, we should set TCR2's divider, not RCR2's divider.Signed-off-by: Shengjiu Wang
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The bclk caculation should according to the slot num, not the channels.
Because sometime we have two slots, but only one slot is enabled for mono
channel.
As when the codec wm8962 works on mono mode, it needs two slots I2S signal.
So here set the default slots of sai to 2, and add function set_tdm_slots for
future usage.Signed-off-by: Shengjiu Wang
11 Dec, 2014
1 commit
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The kernel log is
[] (__dabt_svc+0x38/0x60) from [] (mutex_lock+0xc/0x4c)
[] (mutex_lock+0xc/0x4c) from [] (snd_soc_dapm_stream_event+0x20/0xe4)
[] (snd_soc_dapm_stream_event+0x20/0xe4) from [] (close_delayed_work+0x3c/0x48)
[] (close_delayed_work+0x3c/0x48) from [] (process_one_work+0xfc/0x34c)
[] (process_one_work+0xfc/0x34c) from [] (worker_thread+0x144/0x3a4)
[] (worker_thread+0x144/0x3a4) from [] (kthread+0xa4/0xb0)
[] (kthread+0xa4/0xb0) from [] (ret_from_fork+0x14/0x3c)The alsa driver use shedule_delayed_work when close pcm in remove module.
But after remove module the resource is released, so there will be kernel dump.
So here use ignore_pmdown_time to avoid to use shedule_delayed_work, then this
issue can be avoided.Signed-off-by: Shengjiu Wang
10 Nov, 2014
2 commits
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There is very low possibility that channel swap happened in beginning when
multi output/input pin is enabled. The issue is that hardware can't send data
to correct pin in the begginning with the normal enable flow.
Here use TSMA/TSMB as the trigger for sending data to workaround this issue.Signed-off-by: Shengjiu Wang
(cherry picked from commit 859b0fc4544bef30e269b4f6a81999db1d07a42d) -
When test with case arecord -Dhw:0,1 | aplay -Dhw:0,0, xrun happened,
the reset handler will be called, but for BE(backend) stream, the
substream->ops is null.
This patch is to fix this null pointer issue.Signed-off-by: Shengjiu Wang
(cherry picked from commit 4db112a8cd3caf5a553afea88cf7fe8d9781f459)
03 Nov, 2014
2 commits
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In the frame_to_bytes(), when hw_ptr*frame_bits exceed the maxmum of unsigned
long, the return value is saturated, so the appl_bytes is wrong.
This patch is to correct the usage of frame_to_bytes().Signed-off-by: Shengjiu Wang
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Revert "ENGR00320849-3 ASoC: dmaengine: Audio suspend/resume will be failed."
This reverts commit 2e516e0787f9f83003a2fddac2ce1ce51bbdcfcc.
According commit 1880fc41df, sdma has fixed the issue in suspend/resume. So
enable the audio dma suspend/resume.Signed-off-by: Shengjiu Wang
28 Oct, 2014
14 commits
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Implement machine driver for mqs, which use the sai as cpu dai.
sai work on master mode.Signed-off-by: Shengjiu Wang
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Implement codec driver for mqs. mqs is a very simple IP. which support:
Word length: 16bit.
DAI format: Left-Justified, slave mode.Signed-off-by: Shengjiu Wang
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After several open/close sai test with ctrl+c, there will be I/O error.
The SAI can't work anymore, can't recover. There will be no frame clock.
With adding the software reset in trigger stop, the issue can be fixed.Signed-off-by: Shengjiu Wang
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SAI has 4 mclk source, and the divider is 8bit. fsl_sai_set_bclk will
select proper mclk source and calculate the divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and
add hw_free() to disable the mclk.Signed-off-by: Shengjiu Wang
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There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 855675f6e6a65688a7f4cf45b9b5a98cf6c6f5c3) -
The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added
new Device Tree bindings for Asynchronous and Synchronous modes support.
However, these two shall not be present at the same time.So this patch just simply makes them exclusive so as to avoid incorrect
Device Tree binding usage.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit ce7344a4ebabe90e064d3e087727f45624cdc942) -
SAI supports these operation modes:
1) asynchronous mode
Both Tx and Rx are set to be asynchronous.
2) synchronous mode (Rx sync with Tx)
Tx is set to be asynchronous, Rx is set to be synchronous.
3) synchronous mode (Tx sync with Rx)
Rx is set to be asynchronous, Tx is set to be synchronous.
4) synchronous mode (Tx/Rx sync with another SAI's Tx)
5) synchronous mode (Tx/Rx sync with another SAI's Rx)* 4) and 5) are beyond this patch because they are related with another SAI.
As the initial version of this SAI driver, it supported 2) as default while
the others were totally missing.So this patch just adds supports for 1) and 3).
Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 08fdf65e37d560581233e06a659f73deeb3766f9) -
There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit af96ff5b7448dc776dc24a5c4313c6ec1ee94e53) -
This patch adds software reset code in dai_probe() so as to make a true init
by clearing SAI's internal logic, including the bit clock generation, status
flags, and FIFO pointers.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 376d1a92ca587d3974d4791cdb99baa8b8e7f0dd) -
The previous enable flow:
1, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO)
2, Mask IRQ of Tx/Rx to enable its interrupt.
3, Enable DMA request of Tx/Rx.As this flow would enable DMA request later than TERE, the Tx FIFO
would be easily emptied into underrun while Rx FIFO would be easily
stuffed into overrun due to the delayed DMA transfering.This issue happened merely occational before the patch 'ASoC: fsl_sai:
Reset FIFOs after disabling TE/RE' because there were useless data
remaining in the FIFO for the gap. However, it manifested after FIFO
reset's implemented.After this patch, the new flow:
1, Enable DMA request of Tx/Rx.
2, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO)
3, Mask IRQ of Tx/Rx to enable its interrupt.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit a3fdc6749edf4dcb07df3a10bbdd9850ed5fd01a) -
TE/RE bit of T/RCSR will remain set untill the current frame is physically
finished. The FIFO reset operation should wait this bit's totally cleared
rather than ignoring its status which might cause TE/RE disabling failed.This patch adds delay and timeout to wait for its completion before FIFO
reset.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit c44b56af9ca3a6f135d8f22b9a240f53909b371e) -
For trigger start, we don't need to check if it's the first time to
enable TE/RE or second time. It doesn't hurt to enable them any way,
which in the meantime can reduce race condition for TE/RE enabling.For trigger stop, we will definitely clear FRDE of current direction.
Thus the driver only needs to read the opposite one's.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit f4075a8f452aff5465c6522c92da9db71ed11b7f) -
In the rx irq handling part, we should clear the flags in RCSR not TCSR.
Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 4800f88b615f194ae3c1577038a7ccd871c907c9) -
SAI will not clear their FIFOs after disabling TE/RE. Therfore, the driver
should take care the task so as not to let useless data remain in the FIFO.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit eff952b733d4c1ff3a6b35accce940b223372978)
15 Oct, 2014
4 commits
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Baudclk is esai_extal, which is set CLK_SET_PARENT_GATE flags, so when
the clock is enabled, we can't change the rate later. As we will change the
rate in fsl_ssi_set_bclk(), so remove the enable and disable to hw_params()
and hw_free().Signed-off-by: Shengjiu Wang
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Merge the 8dd51e23a1ef3b5f22eeff4827260b75bafba620 from upstream.
The fsl_ssi driver uses the .set_sysclk callback to configure the
bitclock for master mode. This is unnecessary since the bitclock
is known in hw_params. This patch configures the bitclock from .hw_params.
.set_dai_sysclk now sets a bitclock frequency which is preferred over
the default calculated bitclock frequency.Signed-off-by: Shengjiu Wang
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Configure the aumux port to output SRCK and SRFS from STCK and STFS
of internal port when use the SYN mode.Signed-off-by: Shengjiu Wang
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As the codec_name has a suffix, which is a index and is different
for different platform or different kernel. So here change machine driver
to use codec_of_node, which can be same for different platform/kernel,
then we can maintain a same machine driver for fm.Signed-off-by: Shengjiu Wang
28 Aug, 2014
13 commits
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HDMI isfr clock source from video 27M clock.
There are one clock gate control of video27m_root in CCM,
ccm_video27m_root_cg = ((lpcg_mipi_core_cfg_clk_enable_clock_root
| lpcg_mipi_core_pll_refclk_enable_clock_root) | lpcg_vpu_rclk_enable_clock_root);
The video 27M clock depend on vpu clock or mipi core clock.In mx6 chip, vpu can been disabled by fuse,
so for vpu disabled case, mipi core clock should enabled and make sure
27M clock on.Add mipi core clock management in hdmi drivers to support vpu disabled
case.Signed-off-by: Sandor Yu
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The SRPC register should be volatile, LOCK bit is set by the hardware.
Signed-off-by: Shengjiu Wang
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SDMA suspend/resume is not good enough to support audio suspend/resume.
So disable audio suspend/resume temporarily.Revert "ENGR00318773-5 ASoC: dmaengine: Merge trigger RESUME to START and SUSPEND to STOP"
This reverts commit 29a807b337b0e74460fd3ec699e54eb61183279a.
Signed-off-by: Shengjiu Wang
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When test asrc p2p first, then test no asrc p2p, There is no
sound after 5s. The reason is that the substream is not same for
this two case, then delay powerdown will close the widget for cs42888.
But the second will also use the cs42888. So set ignore_pmdown_time
to 1.Signed-off-by: Shengjiu Wang
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Failed case:
arecord -Dhw:0,1 -f S16_LE -r 96000 -c 2 -traw | aplay -Dhw:0,0 -f
S16_LE -r 96000 -c 2 -traw.
There is no sound when use this case.The reason is that the setting
of Functional mode is not correct.Signed-off-by: Shengjiu Wang
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The upstream version of DAPM routes results record noise issue due to its
inappropriate power-up sequence. So we provisionally revert this change
to the old stable one, and figure out why the sequence has problem later.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
Not only SIS but also other read-only or write-only reigsters should be marked
as volatile register so as not to let regcache cache them. So this patch just
adds those missing registers.Signed-off-by: Nicolin Chen
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The reason is that PRRC and PCRC isn't cleared in restore_reg(), then
update_bits for PCRC and PRRC will fail for cache is not updated.
In other side, remove the store_reg() and restore_reg for adding regcache,
and use regcache_sync to restore the registers.Signed-off-by: Shengjiu Wang
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For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, AUDMUX needs to
save all the values of registers before the system suspend and restore them
after the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SSI needs to save
all the values of registers before the system suspend and restore them after
the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SPDIF needs to save
all the values of registers before the system suspend and restore them after
the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, ESAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
