Eric Lee / smarc-fsl-linux-kernel

05 Jan, 2012

1 commit

22 Aug, 2011

1 commit

04 Mar, 2011

1 commit

20 Oct, 2010

1 commit

  • 6451d7783   arm: remove machine_desc.io_pg_offst and .phys_io ... Browse Code »

    Since we're now using addruart to establish the debug mapping, we can
    remove the io_pg_offst and phys_io members of struct machine_desc.

    The various declarations were removed using the following script:

    grep -rl MACHINE_START arch/arm | xargs \
    sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }'

    [ Initial patch was from Jeremy Kerr, example script from Russell King ]

    Signed-off-by: Nicolas Pitre
    Acked-by: Eric Miao

    Nicolas Pitre
     

17 Jul, 2010

1 commit

09 Jun, 2009

1 commit

29 Mar, 2009

1 commit

22 Mar, 2009

1 commit

  • e84665c9c   dsa: add switch chip cascading support ... Browse Code »

    The initial version of the DSA driver only supported a single switch
    chip per network interface, while DSA-capable switch chips can be
    interconnected to form a tree of switch chips. This patch adds support
    for multiple switch chips on a network interface.

    An example topology for a 16-port device with an embedded CPU is as
    follows:

    +-----+ +--------+ +--------+
    | |eth0 10| switch |9 10| switch |
    | CPU +----------+ +-------+ |
    | | | chip 0 | | chip 1 |
    +-----+ +---++---+ +---++---+
    || ||
    || ||
    ||1000baseT ||1000baseT
    ||ports 1-8 ||ports 9-16

    This requires a couple of interdependent changes in the DSA layer:

    - The dsa platform driver data needs to be extended: there is still
    only one netdevice per DSA driver instance (eth0 in the example
    above), but each of the switch chips in the tree needs its own
    mii_bus device pointer, MII management bus address, and port name
    array. (include/net/dsa.h) The existing in-tree dsa users need
    some small changes to deal with this. (arch/arm)

    - The DSA and Ethertype DSA tagging modules need to be extended to
    use the DSA device ID field on receive and demultiplex the packet
    accordingly, and fill in the DSA device ID field on transmit
    according to which switch chip the packet is heading to.
    (net/dsa/tag_{dsa,edsa}.c)

    - The concept of "CPU port", which is the switch chip port that the
    CPU is connected to (port 10 on switch chip 0 in the example), needs
    to be extended with the concept of "upstream port", which is the
    port on the switch chip that will bring us one hop closer to the CPU
    (port 10 for both switch chips in the example above).

    - The dsa platform data needs to specify which ports on which switch
    chips are links to other switch chips, so that we can enable DSA
    tagging mode on them. (For inter-switch links, we always use
    non-EtherType DSA tagging, since it has lower overhead. The CPU
    link uses dsa or edsa tagging depending on what the 'root' switch
    chip supports.) This is done by specifying "dsa" for the given
    port in the port array.

    - The dsa platform data needs to be extended with information on via
    which port to reach any given switch chip from any given switch chip.
    This info is specified via the per-switch chip data struct ->rtable[]
    array, which gives the nexthop ports for each of the other switches
    in the tree.

    For the example topology above, the dsa platform data would look
    something like this:

    static struct dsa_chip_data sw[2] = {
    {
    .mii_bus = &foo,
    .sw_addr = 1,
    .port_names[0] = "p1",
    .port_names[1] = "p2",
    .port_names[2] = "p3",
    .port_names[3] = "p4",
    .port_names[4] = "p5",
    .port_names[5] = "p6",
    .port_names[6] = "p7",
    .port_names[7] = "p8",
    .port_names[9] = "dsa",
    .port_names[10] = "cpu",
    .rtable = (s8 []){ -1, 9, },
    }, {
    .mii_bus = &foo,
    .sw_addr = 2,
    .port_names[0] = "p9",
    .port_names[1] = "p10",
    .port_names[2] = "p11",
    .port_names[3] = "p12",
    .port_names[4] = "p13",
    .port_names[5] = "p14",
    .port_names[6] = "p15",
    .port_names[7] = "p16",
    .port_names[10] = "dsa",
    .rtable = (s8 []){ 10, -1, },
    },
    },

    static struct dsa_platform_data pd = {
    .netdev = &foo,
    .nr_switches = 2,
    .sw = sw,
    };

    Signed-off-by: Lennert Buytenhek
    Tested-by: Gary Thomas
    Signed-off-by: David S. Miller

    Lennert Buytenhek
     

27 Feb, 2009

3 commits

20 Feb, 2009

1 commit

12 Dec, 2008

1 commit

  • 37787e449   [ARM] Kirkwood: properly handle the WAN port on newer RD88F6281 boards ... Browse Code »

    On newer versions of the RD88F6281 board, the WAN port is connected to
    its own ethernet port on the CPU, via a separate PHY, whereas on older
    versions of the board, it is connected to one of the PHYs in the
    ethernet switch. In the RD8F6281 setup code, detect which version of
    the board we are running on, and instantiate the ethernet ports and
    switch driver accordingly.

    Signed-off-by: Ronen Shitrit
    Signed-off-by: Lennert Buytenhek
    Signed-off-by: Nicolas Pitre

    Ronen Shitrit
     

20 Oct, 2008

1 commit

  • dcf1cece1   [ARM] Orion: instantiate the dsa switch driver ... Browse Code »

    This adds DSA switch instantiation hooks to the orion5x and the
    kirkwood ARM SoC platform code, and instantiates the DSA switch
    driver on the 88F5181L FXO RD, the 88F5181L GE RD, the 6183 AP GE
    RD, the Linksys WRT350n v2, and the 88F6281 RD boards.

    Signed-off-by: Lennert Buytenhek
    Tested-by: Nicolas Pitre
    Tested-by: Peter van Valderen
    Tested-by: Dirk Teurlings
    Signed-off-by: Nicolas Pitre

    Lennert Buytenhek
     

12 Oct, 2008

1 commit

  • 7cc4e87f9   Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm ... Browse Code »

    * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
    [ARM] 5300/1: fixup spitz reset during boot
    [ARM] 5295/1: make ZONE_DMA optional
    [ARM] 5239/1: Palm Zire 72 power management support
    [ARM] 5298/1: Drop desc_handle_irq()
    [ARM] 5297/1: [KS8695] Fix two compile-time warnings
    [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
    [ARM] pxa: allow multi-machine PCMCIA builds
    [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
    [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
    [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
    [ARM] pxa/zylonite: add support for USB OHCI
    [ARM] ohci-pxa27x: use ioremap() and offset for register access
    [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
    [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
    [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
    [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
    [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
    [ARM] pxa: simplify DMA register definitions
    [ARM] pxa: make additional DCSR bits valid for PXA3xx
    [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
    ...

    Fixed up conflicts in
    arch/arm/mach-versatile/core.c
    sound/soc/pxa/pxa2xx-ac97.c
    sound/soc/pxa/pxa2xx-i2s.c
    manually.

    Linus Torvalds
     

26 Sep, 2008

1 commit

05 Sep, 2008

1 commit

  • ac840605f   mv643xx_eth: remove force_phy_addr field ... Browse Code »

    Currently, there are two different fields in the
    mv643xx_eth_platform_data struct that together describe the PHY
    address -- one field (phy_addr) has the address of the PHY, but if
    that address is zero, a second field (force_phy_addr) needs to be
    set to distinguish the actual address zero from a zero due to not
    having filled in the PHY address explicitly (which should mean
    'use the default PHY address').

    If we are a bit smarter about the encoding of the phy_addr field,
    we can avoid the need for a second field -- this patch does that.

    Signed-off-by: Lennert Buytenhek

    Lennert Buytenhek
     

09 Aug, 2008

1 commit

07 Aug, 2008

1 commit

24 Jul, 2008

1 commit

  • 81600eea9   mv643xx_eth: use auto phy polling for configuring (R)(G)MII interface ... Browse Code »

    The mv643xx_eth hardware has a provision for polling the PHY's
    MII management registers to obtain the (R)(G)MII interface speed
    (10/100/1000) and duplex (half/full) and pause (off/symmetric)
    settings to use to talk to the PHY.

    The driver currently does not make use of this feature. Instead,
    whenever there is a link status change event, it reads the current
    link parameters from the PHY, and programs those parameters into
    the mv643xx_eth MAC by hand.

    This patch switches the mv643xx_eth driver to letting the MAC
    auto-determine the (R)(G)MII link parameters by PHY polling, if there
    is a PHY present. For PHYless ports (when e.g. the (R)(G)MII
    interface is connected to a hardware switch), we keep hardcoding the
    MII interface parameters.

    Signed-off-by: Lennert Buytenhek

    Lennert Buytenhek
     

01 Jul, 2008

1 commit

23 Jun, 2008

1 commit

  • 651c74c74   [ARM] add Marvell Kirkwood (88F6000) SoC support ... Browse Code »

    The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
    Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
    a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
    interface, and IDMA/XOR engines, and depending on the model, also
    features one or two Gigabit Ethernet interfaces, two SATA II
    interfaces, one or two TWSI interfaces, one or two UARTs, a
    TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
    an SDIO interface.

    This patch adds supports for the Marvell DB-88F6281-BP Development
    Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
    enabling support for the PCIe interface, the USB interface, the
    ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
    UARTs, and the NAND controller.

    Signed-off-by: Saeed Bishara
    Signed-off-by: Lennert Buytenhek

    Saeed Bishara