Eric Lee / smarc-fsl-linux-kernel

13 Sep, 2011

1 commit

  • bd31b8596   locking, ARM: Annotate low level hw locks as raw ... Browse Code »

    Annotate the low level hardware locks which must not be preempted.

    In mainline this change documents the low level nature of
    the lock - otherwise there's no functional difference. Lockdep
    and Sparse checking will work as usual.

    Signed-off-by: Thomas Gleixner
    Cc: Russell King
    Signed-off-by: Ingo Molnar

    Thomas Gleixner
     

19 Sep, 2010

1 commit

  • c01778001   ARM: 6379/1: Assume new page cache pages have dirty D-cache ... Browse Code »

    There are places in Linux where writes to newly allocated page cache
    pages happen without a subsequent call to flush_dcache_page() (several
    PIO drivers including USB HCD). This patch changes the meaning of
    PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
    mapped page in update_mmu_cache().

    The patch also sets the PG_arch_1 bit in the DMA cache maintenance
    function to avoid additional cache flushing in update_mmu_cache().

    Tested-by: Rabin Vincent
    Cc: Nicolas Pitre
    Signed-off-by: Catalin Marinas
    Signed-off-by: Russell King

    Catalin Marinas
     

05 Oct, 2009

1 commit

13 Mar, 2009

1 commit

  • 446c92b29   [ARM] 5421/1: ftrace: fix crash due to tracing of __naked functions ... Browse Code »

    This is a fix for the following crash observed in 2.6.29-rc3:
    http://lkml.org/lkml/2009/1/29/150

    On ARM it doesn't make sense to trace a naked function because then
    mcount is called without stack and frame pointer being set up and there
    is no chance to restore the lr register to the value before mcount was
    called.

    Reported-by: Matthias Kaehlcke
    Tested-by: Matthias Kaehlcke

    Cc: Abhishek Sagar
    Cc: Steven Rostedt
    Cc: Ingo Molnar
    Signed-off-by: Uwe Kleine-König
    Signed-off-by: Russell King

    Uwe Kleine-König
     

24 Jan, 2009

1 commit

28 Nov, 2008

3 commits

  • 43ae286b7   [ARM] fix a couple clear_user_highpage assembly constraints ... Browse Code »

    In all cases the kaddr is assigned an input register even though it is
    modified in the assembly code. Let's assign a new variable to the
    modified value and mark those inline asm with volatile otherwise they
    get optimized away because the output variable is otherwise not used.

    Also fix a few conversion errors in copypage-feroceon.c and
    copypage-v4mc.c.

    Signed-off-by: Nicolas Pitre
    Signed-off-by: Russell King

    Nicolas Pitre
     
  • 303c64436   [ARM] clearpage: provide our own clear_user_highpage() ... Browse Code »

    For similar reasons as copy_user_page(), we want to avoid the
    additional kmap_atomic if it's unnecessary.

    Signed-off-by: Russell King

    Russell King
     
  • 063b0a420   [ARM] copypage: provide our own copy_user_highpage() ... Browse Code »

    We used to override the copy_user_page() function. However, this
    is not only inefficient, it also causes additional complexity for
    highmem support, since we convert from a struct page to a kernel
    direct mapped address and back to a struct page again.

    Moreover, with highmem support, we end up pointlessly setting up
    kmap entries for pages which we're going to remap. So, push the
    kmapping down into the copypage implementation files where it's
    required.

    Signed-off-by: Russell King

    Russell King
     

01 Oct, 2008

1 commit

  • bb30f36f9   [ARM] Introduce new PTE memory type bits ... Browse Code »

    Provide L_PTE_MT_xxx definitions to describe the memory types that we
    use in Linux/ARM. These definitions are carefully picked such that:

    1. their LSBs match what is required for pre-ARMv6 CPUs.
    2. they all have a unique encoding, including after modification
    by build_mem_type_table() (the result being that some have more
    than one combination.)

    Signed-off-by: Russell King

    Russell King
     

31 Dec, 2006

1 commit

  • 1c9d3df5e   [ARM] 4078/1: Fix ARM copypage cache coherency problems ... Browse Code »

    If PG_dcache_dirty is set for a page, we need to flush the source page
    before performing any copypage operation using a different virtual address.

    This fixes the copypage implementations for XScale, StrongARM and ARMv6.

    This patch fixes segmentation faults seen in the dynamic linker under
    the usage patterns in glibc 2.4/2.5.

    Signed-off-by: Richard Purdie
    Signed-off-by: Russell King

    Richard Purdie
     

13 Dec, 2006

1 commit

  • ad1ae2fe7   [ARM] Unuse another Linux PTE bit ... Browse Code »

    L_PTE_ASID is not really required to be stored in every PTE, since we
    can identify it via the address passed to set_pte_at(). So, create
    set_pte_ext() which takes the address of the PTE to set, the Linux
    PTE value, and the additional CPU PTE bits which aren't encoded in
    the Linux PTE value.

    Signed-off-by: Russell King

    Russell King
     

20 Sep, 2006

1 commit

17 May, 2005

1 commit

10 May, 2005

1 commit