Eric Lee / smarc-fsl-linux-kernel

06 Dec, 2011

1 commit

09 Aug, 2011

1 commit

  • 7760d5460   ARM: 7005/1: freshen up mm/proc-arm946.S ... Browse Code »

    The file mm/proc-arm946.S contains a typo and is missing a structure
    member in __arm946_proc_info. The former prevents compilation
    and the latter causes problems during boot. It is likely this
    file was manually copied from a similar file and not tested, then
    later updates to the *_proc_info structures missed this file.

    This patch will apply (with offset) with or without the
    recent macro unification work that has been done in this directory.
    This was verified against linux-next/stable last week.

    See arm-linux-kernel thread:
    http://lists.arm.linux.org.uk/lurker/message/20110718.103237.0106d468.en.html

    Signed-off-by: Brian S. Julin
    Signed-off-by: Russell King

    Brian S. Julin
     

07 Jul, 2011

1 commit

23 Feb, 2011

1 commit

  • f6b0fa02e   ARM: pm: add generic CPU suspend/resume support ... Browse Code »

    This adds core support for saving and restoring CPU coprocessor
    registers for suspend/resume support. This contains support for suspend
    with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
    Tested on Assabet and Tegra 2.

    Tested-by: Colin Cross
    Tested-by: Kukjin Kim
    Signed-off-by: Russell King

    Russell King
     

28 Oct, 2010

1 commit

  • c8c90860c   ARM: 6466/1: implement flush_icache_all for the rest of the CPUs ... Browse Code »

    Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for
    CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns:
    flush_icache_all(). It also implemented this for v6 and v7 but not
    for v5 and backwards. Without the function pointer in place, we
    will be calling wrong cache functions.

    For example with ep93xx we get following:

    Unable to handle kernel paging request at virtual address ee070f38
    pgd = c0004000
    [ee070f38] *pgd=00000000
    Internal error: Oops: 80000005 [#1] PREEMPT
    last sysfs file:
    Modules linked in:
    CPU: 0 Not tainted (2.6.36+ #1)
    PC is at 0xee070f38
    LR is at __dma_alloc+0x11c/0x2d0
    pc : [] lr : [] psr: 60000013
    sp : c581bde0 ip : 00000000 fp : c0472000
    r10: c0472000 r9 : 000000d0 r8 : 00020000
    r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000
    r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000
    Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
    Control: c000717f Table: c0004000 DAC: 00000017
    Process swapper (pid: 1, stack limit = 0xc581a270)
    [] (__dma_alloc+0x11c/0x2d0)
    [] (dma_alloc_writecombine+0x1c/0x24)
    [] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60)
    [] (ep93xx_pcm_new+0x5c/0x88)
    [] (snd_soc_instantiate_cards+0x8a8/0xbc0)
    [] (soc_probe+0xfc/0x134)
    [] (platform_drv_probe+0x18/0x1c)
    [] (driver_probe_device+0xb0/0x16c)
    [] (bus_for_each_drv+0x48/0x84)
    [] (device_attach+0x50/0x68)
    [] (bus_probe_device+0x24/0x44)
    [] (device_add+0x2fc/0x44c)
    [] (platform_device_add+0x104/0x15c)
    [] (simone_init+0x60/0x94)
    [] (do_one_initcall+0xd0/0x1a4)

    __dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up
    calling dmac_flush_range(). Now since the entries in the
    arm920_cache_fns are shifted by one, we jump into address 0xee070f38
    which is actually next instruction after the arm920_cache_fns
    structure.

    So implement flush_icache_all() for the rest of the supported CPUs
    using a generic 'invalidate I cache' instruction.

    Signed-off-by: Mika Westerberg
    Signed-off-by: Russell King

    Mika Westerberg
     

08 Oct, 2010

1 commit

27 Jul, 2010

1 commit

  • 9ca03a21e   ARM: Factor out common code from cpu_proc_fin() ... Browse Code »

    All implementations of cpu_proc_fin() start by disabling interrupts
    and then flush caches. Rather than have every processors proc_fin()
    implementation do this, move it out into generic code - and move the
    cache flush past setup_mm_for_reboot() (so it can benefit from having
    caches still enabled.)

    This allows cpu_proc_fin() to become independent of the L1/L2 cache
    types, and eventually move the L2 cache flushing into the L2 support
    code.

    Signed-off-by: Russell King

    Russell King
     

15 Feb, 2010

2 commits

14 Dec, 2009

1 commit

03 Oct, 2009

1 commit

  • 4fb284743   ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() ... Browse Code »

    Instruction fault status register, IFSR, was introduced on ARMv6 to
    provide status information about the last insturction fault. It
    needed for proper prefetch abort handling.

    Now we have three prefetch abort model:

    * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
    * ARMv6 - provides IFSR, but not IFAR;
    * ARMv7 - provides both IFSR and IFAR.

    Signed-off-by: Kirill A. Shutemov
    Signed-off-by: Russell King

    Kirill A. Shutemov
     

01 Oct, 2008

1 commit

13 Aug, 2008

1 commit

18 May, 2008

1 commit

24 Apr, 2008

1 commit

  • 4a1fd556c   [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f ... Browse Code »

    The proc-*.S files have the _prefetch_abort pointer placed at the end
    of the processor structure but the cpu-multi32.h defines it in the
    second position. The patch also fixes the support for XSC3 and the
    MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).

    Signed-off-by: Catalin Marinas
    Signed-off-by: Russell King

    Catalin Marinas
     

30 Nov, 2006

1 commit

29 Sep, 2006

1 commit

  • 0f45d7f36   [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores. ... Browse Code »

    There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a
    dummy abort handler which returns zero for the base restored Data Abort
    model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up
    for the base updated Data Abort model cores.

    Signed-off-by: Hyok S. Choi
    Signed-off-by: Russell King

    Hyok S. Choi
     

28 Sep, 2006

1 commit

  • f37f46eb1   [ARM] nommu: add ARM946E-S core support ... Browse Code »

    This patch adds ARM946E-S core support which has typically 8KB I&D cache.
    It has a MPU and supports ARMv5TE instruction set.

    Because the ARM946E-S core can be synthesizable with various cache size,
    CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations.

    Signed-off-by: Hyok S. Choi
    Signed-off-by: Russell King

    Hyok S. Choi