06 Dec, 2011
1 commit
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The CPU reset functions disable the MMU and therefore must be executed
with an identity mapping in place.This patch places the CPU reset functions into the .idmap.text section,
causing the idmap code to include them as part of the identity mapping.Acked-by: Dave Martin
Signed-off-by: Will Deacon
07 Jul, 2011
1 commit
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Signed-off-by: Dave Martin
Acked-by: Nicolas Pitre
23 Feb, 2011
1 commit
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This adds core support for saving and restoring CPU coprocessor
registers for suspend/resume support. This contains support for suspend
with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
Tested on Assabet and Tegra 2.Tested-by: Colin Cross
Tested-by: Kukjin Kim
Signed-off-by: Russell King
28 Oct, 2010
1 commit
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Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for
CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns:
flush_icache_all(). It also implemented this for v6 and v7 but not
for v5 and backwards. Without the function pointer in place, we
will be calling wrong cache functions.For example with ep93xx we get following:
Unable to handle kernel paging request at virtual address ee070f38
pgd = c0004000
[ee070f38] *pgd=00000000
Internal error: Oops: 80000005 [#1] PREEMPT
last sysfs file:
Modules linked in:
CPU: 0 Not tainted (2.6.36+ #1)
PC is at 0xee070f38
LR is at __dma_alloc+0x11c/0x2d0
pc : [] lr : [] psr: 60000013
sp : c581bde0 ip : 00000000 fp : c0472000
r10: c0472000 r9 : 000000d0 r8 : 00020000
r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000
r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: c000717f Table: c0004000 DAC: 00000017
Process swapper (pid: 1, stack limit = 0xc581a270)
[] (__dma_alloc+0x11c/0x2d0)
[] (dma_alloc_writecombine+0x1c/0x24)
[] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60)
[] (ep93xx_pcm_new+0x5c/0x88)
[] (snd_soc_instantiate_cards+0x8a8/0xbc0)
[] (soc_probe+0xfc/0x134)
[] (platform_drv_probe+0x18/0x1c)
[] (driver_probe_device+0xb0/0x16c)
[] (bus_for_each_drv+0x48/0x84)
[] (device_attach+0x50/0x68)
[] (bus_probe_device+0x24/0x44)
[] (device_add+0x2fc/0x44c)
[] (platform_device_add+0x104/0x15c)
[] (simone_init+0x60/0x94)
[] (do_one_initcall+0xd0/0x1a4)__dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up
calling dmac_flush_range(). Now since the entries in the
arm920_cache_fns are shifted by one, we jump into address 0xee070f38
which is actually next instruction after the arm920_cache_fns
structure.So implement flush_icache_all() for the rest of the supported CPUs
using a generic 'invalidate I cache' instruction.Signed-off-by: Mika Westerberg
Signed-off-by: Russell King
08 Oct, 2010
1 commit
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When hotplug CPU is enabled, we need to keep the list of supported CPUs,
their setup functions, and __lookup_processor_type in place so that we
can find and initialize secondary CPUs. Move these into the __CPUINIT
section.Signed-off-by: Russell King
27 Jul, 2010
1 commit
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All implementations of cpu_proc_fin() start by disabling interrupts
and then flush caches. Rather than have every processors proc_fin()
implementation do this, move it out into generic code - and move the
cache flush past setup_mm_for_reboot() (so it can benefit from having
caches still enabled.)This allows cpu_proc_fin() to become independent of the L1/L2 cache
types, and eventually move the L2 cache flushing into the L2 support
code.Signed-off-by: Russell King
15 Feb, 2010
2 commits
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These are now unused, and so can be removed.
Signed-off-by: Russell King
Tested-By: Santosh Shilimkar -
Signed-off-by: Russell King
Tested-By: Santosh Shilimkar
14 Dec, 2009
1 commit
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... and rename the function since it no longer operates on just
pages.Signed-off-by: Russell King
03 Oct, 2009
1 commit
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Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.Now we have three prefetch abort model:
* legacy - for CPUs before ARMv6. They doesn't provide neither
IFSR nor IFAR. We simulate IFSR with section translation fault
status for them to generalize code;
* ARMv6 - provides IFSR, but not IFAR;
* ARMv7 - provides both IFSR and IFAR.Signed-off-by: Kirill A. Shutemov
Signed-off-by: Russell King
10 Oct, 2008
1 commit
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Merge branch 'orion-devel' into devel
01 Oct, 2008
2 commits
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asm code really wants asm/hwcap.h, so include that instead.
Signed-off-by: Russell King
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There are actually only four separate implementations of set_pte_ext.
Use assembler macros to insert code for these into the proc-*.S files.Signed-off-by: Russell King
26 Sep, 2008
1 commit
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Feroceon L2 cache can work in eighther write through or write back mode
on Kirkwood. Add the option to configure this mode according to Kconfig.Signed-off-by: Ronen Shitrit
Signed-off-by: Nicolas Pitre
08 Jul, 2008
1 commit
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On Feroceon platforms that have a branch prediction unit, bit 11 of the
cp15 control register controls the BPU. This patch keeps the old value
of this bit instead of always clearing it.Signed-off-by: Saeed Bishara
Signed-off-by: Lennert Buytenhek
Signed-off-by: Nicolas Pitre
23 Jun, 2008
8 commits
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Add support for the Feroceon 88fr571-vd CPU core as found in e.g.
the Marvell Discovery Duo family of ARM SoCs.Signed-off-by: Lennert Buytenhek
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Add support for the Shiva 88fr131 CPU core as found in e.g. the
Marvell Kirkwood family of ARM SoCs.Signed-off-by: Lennert Buytenhek
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This patch adds support for the unified Feroceon L2 cache controller
as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
families of ARM SoCs.Note that:
- Page table walks are outer uncacheable on Kirkwood and Discovery
Duo, since the ARMv5 spec provides no way to indicate outer
cacheability of page table walks (specifying it in TTBR[4:3] is
an ARMv6+ feature).This requires adding L2 cache clean instructions to
proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled
by defining a new TLB type (TLB_FEROCEON) which is almost identical
to the v4wbi one but provides a TLB_L2CLEAN_FR flag.- The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
range by MVA' and 'invalidate L2 range by MVA') operations, and this
patch uses those range operations for all Linux outer cache
operations, as they are faster than the regular per-line operations.L2 range operations are not interruptible on this hardware, which
avoids potential livelock issues, but can be bad for interrupt
latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
allows you to select the maximum range size to operate on at once.
(Valid range is between one cache line and one 4KiB page, and must
be a multiple of the line size.)Signed-off-by: Lennert Buytenhek
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This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.Signed-off-by: Stanislav Samsonov
Acked-by: Saeed Bishara
Reviewed-by: Nicolas Pitre
Signed-off-by: Lennert Buytenhek -
There are a couple more Feroceon-based SoCs out in the field that use
different Variant and Architecture fields in their Main ID registers
-- this patch tweaks the processor match/mask in proc-feroceon.S to
catch those SoCs as well.Signed-off-by: Ke Wei
Signed-off-by: Lennert Buytenhek -
Flushing the L1 D cache with a test/clean/invalidate loop is very
easy in software, but it is not the quickest way of doing it, as
there is a lot of overhead involved in re-scanning the cache from
the beginning every time we hit a dirty line.This patch makes proc-feroceon.S use "clean+invalidate by set/way"
loops according to possible cache configuration of Feroceon CPUs
(either direct-mapped or 4-way set associative).Signed-off-by: Nicolas Pitre
Signed-off-by: Lennert Buytenhek -
Annotate the entries for the 88fr531-vd CPU core in
arch/arm/boot/compressed/head.S and arch/arm/mm/proc-feroceon.S
with the full name of the core.Signed-off-by: Lennert Buytenhek
Acked-by: Russell King -
More cosmetic cleanup:
- Replace 8-space indents by proper tab indents.
- In structure initialisers, use a trailing comma for every member.
- Collapse "},\n{" in structure initialiers to "}, {".Signed-off-by: Lennert Buytenhek
Acked-by: Russell King
29 Apr, 2008
4 commits
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This patch implements a set of Feroceon-specific
{copy,clear}_user_page() routines that perform more optimally than
the generic implementations. This also deals with write-allocate
caches (Feroceon can run L1 D in WA mode) which otherwise prevents
Linux from booting.[nico: optimized the code even further]
Signed-off-by: Lennert Buytenhek
Tested-by: Sylver Bruneau
Tested-by: Martin Michlmayr
Signed-off-by: Nicolas Pitre -
One overzealous .align 10 fixed, and a few .align5 added.
Signed-off-by: Nicolas Pitre
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Since the Feroceon cache replacement policy is always pseudorandom
(and the relevant control register bit is ignored), remove the
CONFIG_CPU_CACHE_ROUND_ROBIN check from proc-feroceon.S.Signed-off-by: Lennert Buytenhek
Signed-off-by: Nicolas Pitre -
Since the Feroceon doesn't have a global WT override bit like
ARM926 does, remove all code relating to this mode of operation
from proc-feroceon.S.Signed-off-by: Lennert Buytenhek
Signed-off-by: Nicolas Pitre
24 Apr, 2008
1 commit
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The proc-*.S files have the _prefetch_abort pointer placed at the end
of the processor structure but the cpu-multi32.h defines it in the
second position. The patch also fixes the support for XSC3 and the
MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
19 Apr, 2008
1 commit
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This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.Signed-off-by: Paul Brook
Signed-off-by: Catalin Marinas
26 Jan, 2008
2 commits
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This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and old Feroceon-2850.Signed-off-by: Tzachi Perelstein
Signed-off-by: Nicolas Pitre
Acked-by: Russell King -
The Feroceon is a family of independent ARMv5TE compliant CPU core
implementations, supporting a variable depth pipeline and out-of-order
execution. The Feroceon is configurable with VFP support, and the
later models in the series are superscalar with up to two instructions
per clock cycle.This patch adds the initial low-level cache/TLB handling for this core.
Signed-off-by: Assaf Hoffman
Reviewed-by: Tzachi Perelstein
Reviewed-by: Nicolas Pitre
Reviewed-by: Lennert Buytenhek
Acked-by: Russell King
