10 Jan, 2011
1 commit
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When using an uncached DMA region less than 1 MiB, we try to mask off
the whole last 1 MiB for it. Unfortunately, this fails as we forgot
to subtract one from the calculated mask, leading to the region still
be marked as cacheable.Reported-by: Andrew Rook
Signed-off-by: Sonic Zhang
Signed-off-by: Mike Frysinger
09 Mar, 2010
1 commit
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Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger
15 Dec, 2009
2 commits
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Normally there is no user-reserved memory after the DMA region which means
there is no user-reserved ICPLB coverage. So the DMA hole can be covered
by the large hole that is always added to cover up to the async bank. We
only need an explicit DMA whole when we also add an explicit mapping for
the user-reserved memory.Signed-off-by: Mike Frysinger
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When working with 8 meg systems, forcing a 1 meg DMA chunk heavily cuts
into the available resources. So support smaller chunks to better cover
needs for these systems.Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger
07 Oct, 2009
1 commit
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Bill Gatliff & David Brownell pointed out we were missing some
copyrights, and licensing terms in some of the files in
./arch/blackfin, so this fixes things, and cleans them up.It also removes:
- verbose GPL text(refer to the top level ./COPYING file)
- file names (you are looking at the file)
- bug url (it's in the ./MAINTAINERS file)
- "or later" on GPL-2, when we did not have that rightIt also allows some Blackfin-specific assembly files to be under a BSD
like license (for people to use them outside of Linux).Signed-off-by: Robin Getz
Signed-off-by: Mike Frysinger
17 Sep, 2009
4 commits
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The CPLB implementations (mpu/nompu) had exact copies of the cacheinit
code. Even the i/d cache functions are largely the same. So unify them
both in the common kernel cache code.Signed-off-by: Mike Frysinger
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When doing XIP, we need to execute out of the async banks, so we need
ICPLBs to allow this.Signed-off-by: Bernd Schmidt
Signed-off-by: Mike Frysinger -
When preempt debugging is enabled, smp_processor_id() may utilize the
"current" structure. This may not be safe to access under all exceptions
due to it being in dynamically allocated memory. So in exception code,
make sure we use raw_smp_processor_id() instead to get at the real value
directly.Signed-off-by: Yi Li
Signed-off-by: Mike Frysinger -
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper
sync procedures as laid out in the Blackfin programming manual. So rather
than audit/fix every call location, create helper functions that do the
right things in order to safely update these MMRs. Then convert all call
sites to use these new helper functions.While we're fixing the code, drop the workaround for anomaly 05000125 as
that anomaly applies to old versions of silicon that we do not support.Signed-off-by: Yi Li
Signed-off-by: Mike Frysinger
16 Jul, 2009
1 commit
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The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions. Any code that attempted to use these would wrongly crash due to
a CPLB miss.Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger
13 Jun, 2009
1 commit
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We don't need to handle CPLB protection violations unless we are running
with the MPU on. Fix the entry code to call common trap_c, and remove the
code which is never run. This allows the traps test suite to run on older
boards with the MPU disabled.URL: http://blackfin.uclinux.org/gf/tracker/5129
Signed-off-by: Robin Getz
Signed-off-by: Mike Frysinger
12 Jun, 2009
1 commit
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Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger
02 Mar, 2009
1 commit
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The nompu code is now derived from the mpu code, and had the same problem -
no null pointer detection on ICPLBs.Signed-off-by: Bernd Schmidt
Cc: Mike Frysinger
Signed-off-by: Bryan Wu
04 Feb, 2009
1 commit
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use a do...while loop rather than a for loop to get slightly better
optimization and to avoid gcc "may be used uninitialized" warnings ...
we know that the [id]cplb_nr_bounds variables will never be 0, so this
is OKSigned-off-by: Mike Frysinger
Signed-off-by: Bryan Wu
07 Jan, 2009
3 commits
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This is a mixture ofcMichael McTernan's patch and the existing cplb-mpu code.
We ditch the old cplb-nompu implementation, which is a good example of
why a good algorithm in a HLL is preferrable to a bad algorithm written in
assembly. Rather than try to construct a table of all posible CPLBs and
search it, we just create a (smaller) table of memory regions and
their attributes. Some of the data structures are now unified for both
the mpu and nompu cases. A lot of needless complexity in cplbinit.c is
removed.Further optimizations:
* compile cplbmgr.c with a lot of -ffixed-reg options, and omit saving
these registers on the stack when entering a CPLB exception.
* lose cli/nop/nop/sti sequences for some workarounds - these don't
* make
sense in an exception contextAdditional code unification should be possible after this.
[Mike Frysinger :
- convert CPP if statements to C if statements
- remove redundant statements
- use a do...while loop rather than a for loop to get slightly better
optimization and to avoid gcc "may be used uninitialized" warnings ...
we know that the [id]cplb_nr_bounds variables will never be 0, so this
is OK
- the no-mpu code was the last user of MAX_MEM_SIZE and with that rewritten,
we can punt it
- add some BUG_ON() checks to make sure we dont overflow the small
cplb_bounds array
- add i/d cplb entries for the bootrom because there is functions/data in
there we want to access
- we do not need a NULL trailing entry as any time we access the bounds
arrays, we use the nr_bounds variable
]Signed-off-by: Michael McTernan
Signed-off-by: Mike Frysinger
Signed-off-by: Bernd Schmidt
Signed-off-by: Bryan Wu -
1. Use inline get_l1_... functions instead of macro
2. Fix compile issue about smp barrier functionsSigned-off-by: Graf Yang
Signed-off-by: Bryan Wu -
Tweak the BUG_ON() check to allow for equal values since the way pos is
handled ... it is always indexed and post incrementedSigned-off-by: Mike Frysinger
Signed-off-by: Bryan Wu
18 Nov, 2008
7 commits
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Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu -
- unify duplicate page_size_table definitions
- make sure it is placed alongside the other cplb switching codePointed-out-by: Michael McTernan
Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu -
Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu -
change return of close_cplbtab() and fill_cplbtab() to void since we
always return 0 and nowhere do we check thisSigned-off-by: Mike Frysinger
Signed-off-by: Bryan Wu -
Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu -
Merge MPU and noMPU version of CPLB info code to one common version.
Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu -
Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-likeIn this patch, we provide SMP extend to Blackfin CPLB related code
Signed-off-by: Graf Yang
Signed-off-by: Bryan Wu
27 Oct, 2008
1 commit
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only if the cplb block overlapped with kernel area, this cplb need be locked
Signed-off-by: Graf Yang
Signed-off-by: Bryan Wu
16 Oct, 2008
1 commit
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Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu
09 Oct, 2008
1 commit
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Signed-off-by: Sonic Zhang
Signed-off-by: Bryan Wu
08 Oct, 2008
1 commit
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Signed-off-by: Graf Yang
Signed-off-by: Bryan Wu
14 Aug, 2008
1 commit
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Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu
13 Aug, 2008
1 commit
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Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu
15 Jul, 2008
1 commit
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Use long jump
Signed-off-by: Michael Hennerich
Signed-off-by: Bryan Wu
14 Jul, 2008
1 commit
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use kernel command line mem and max_mem bootargs to limit
availabe memory instead.Signed-off-by: Michael Hennerich
Signed-off-by: Bryan Wu
25 Jun, 2008
1 commit
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--
WARNING: vmlinux.o(.text+0x721a): Section mismatch in reference from the function ___fill_code_cplbtab() to the function .init.text:_fill_cplbtab()
The function ___fill_code_cplbtab() references
the function __init _fill_cplbtab().
This is often because ___fill_code_cplbtab lacks a __init
annotation or the annotation of _fill_cplbtab is wrong.WARNING: vmlinux.o(.text+0x7238): Section mismatch in reference from the function ___fill_code_cplbtab() to the function .init.text:_fill_cplbtab()
The function ___fill_code_cplbtab() references
the function __init _fill_cplbtab().
This is often because ___fill_code_cplbtab lacks a __init
annotation or the annotation of _fill_cplbtab is wrong.WARNING: vmlinux.o(.text+0x7250): Section mismatch in reference from the function ___fill_code_cplbtab() to the function .init.text:_fill_cplbtab()
The function ___fill_code_cplbtab() references
the function __init _fill_cplbtab().
This is often because ___fill_code_cplbtab lacks a __init
annotation or the annotation of _fill_cplbtab is wrong.WARNING: vmlinux.o(.text+0x7264): Section mismatch in reference from the function ___fill_code_cplbtab() to the function .init.text:_fill_cplbtab()
The function ___fill_code_cplbtab() references
the function __init _fill_cplbtab().
This is often because ___fill_code_cplbtab lacks a __init
annotation or the annotation of _fill_cplbtab is wrong.WARNING: vmlinux.o(.text+0x72a2): Section mismatch in reference from the function ___fill_data_cplbtab() to the function .init.text:_fill_cplbtab()
The function ___fill_data_cplbtab() references
the function __init _fill_cplbtab().
This is often because ___fill_data_cplbtab lacks a __init
annotation or the annotation of _fill_cplbtab is wrong.WARNING: vmlinux.o(.text+0x72bc): Section mismatch in reference from the function ___fill_data_cplbtab() to the function .init.text:_fill_cplbtab()
The function ___fill_data_cplbtab() references
the function __init _fill_cplbtab().
This is often because ___fill_data_cplbtab lacks a __init
annotation or the annotation of _fill_cplbtab is wrong.WARNING: vmlinux.o(.text+0x72d4): Section mismatch in reference from the function ___fill_data_cplbtab() to the function .init.text:_fill_cplbtab()
The function ___fill_data_cplbtab() references
the function __init _fill_cplbtab().
This is often because ___fill_data_cplbtab lacks a __init
annotation or the annotation of _fill_cplbtab is wrong.WARNING: vmlinux.o(.text+0x72e8): Section mismatch in reference from the function ___fill_data_cplbtab() to the function .init.text:_fill_cplbtab()
The function ___fill_data_cplbtab() references
the function __init _fill_cplbtab().
This is often because ___fill_data_cplbtab lacks a __init
annotation or the annotation of _fill_cplbtab is wrong.
--Signed-off-by: Bryan Wu
25 Apr, 2008
1 commit
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detect the memory available in the system on the fly by default
rather than forcing people to set this manually in the kconfigSigned-off-by: Mike Frysinger
Signed-off-by: Bryan Wu
24 Apr, 2008
2 commits
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Signed-off-by: Mike Frysinger
Signed-off-by: Bryan Wu -
…the global blackfin header
remove duplicated prototypes for internal cplb structures from
the global blackfin header as nothing else should be accessing theseSigned-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
23 Apr, 2008
1 commit
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…re it actually gets used.
relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file
where it actually gets used. this way when we change
CONFIG_MEM_SIZE in our kconfig, we only rebuild one or two files
rather than a whole bunch that implicitly include cplb.h.this will also remove the ability to clear the swapcount on
the fly, but i really dont think that functionality is important.ultimate goal is for CONFIG_MEM_SIZE to go away and calculate
this value on the fly based on what u-boot programmed for us.Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
22 Jan, 2008
1 commit
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writes to I/DMEM_CONTROL must be followed by SSYNC
Signed-off-by: Michael Hennerich
Signed-off-by: Bryan Wu
11 Jan, 2008
1 commit
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Signed-off-by: Bernd Schmidt
Signed-off-by: Bryan Wu