Eric Lee / smarc-fsl-linux-kernel

02 Sep, 2010

1 commit

22 Jun, 2010

1 commit

  • 0016a4cf5   powerpc: Emulate most Book I instructions in emulate_step() ... Browse Code »

    This extends the emulate_step() function to handle a large proportion
    of the Book I instructions implemented on current 64-bit server
    processors. The aim is to handle all the load and store instructions
    used in the kernel, plus all of the instructions that appear between
    l[wd]arx and st[wd]cx., so this handles the Altivec/VMX lvx and stvx
    and the VSX lxv2dx and stxv2dx instructions (implemented in POWER7).

    The new code can emulate user mode instructions, and checks the
    effective address for a load or store if the saved state is for
    user mode. It doesn't handle little-endian mode at present.

    For floating-point, Altivec/VMX and VSX instructions, it checks
    that the saved MSR has the enable bit for the relevant facility
    set, and if so, assumes that the FP/VMX/VSX registers contain
    valid state, and does loads or stores directly to/from the
    FP/VMX/VSX registers, using assembly helpers in ldstfp.S.

    Instructions supported now include:
    * Loads and stores, including some but not all VMX and VSX instructions,
    and lmw/stmw
    * Atomic loads and stores (l[dw]arx, st[dw]cx.)
    * Arithmetic instructions (add, subtract, multiply, divide, etc.)
    * Compare instructions
    * Rotate and mask instructions
    * Shift instructions
    * Logical instructions (and, or, xor, etc.)
    * Condition register logical instructions
    * mtcrf, cntlz[wd], exts[bhw]
    * isync, sync, lwsync, ptesync, eieio
    * Cache operations (dcbf, dcbst, dcbt, dcbtst)

    The overflow-checking arithmetic instructions are not included, but
    they appear not to be ever used in C code.

    This uses decimal values for the minor opcodes in the switch statements
    because that is what appears in the Power ISA specification, thus it is
    easier to check that they are correct if they are in decimal.

    If this is used to single-step an instruction where a data breakpoint
    interrupt occurred, then there is the possibility that the instruction
    is a lwarx or ldarx. In that case we have to be careful not to lose the
    reservation until we get to the matching st[wd]cx., or we'll never make
    forward progress. One alternative is to try to arrange that we can
    return from interrupts and handle data breakpoint interrupts without
    losing the reservation, which means not using any spinlocks, mutexes,
    or atomic ops (including bitops). That seems rather fragile. The
    other alternative is to emulate the larx/stcx and all the instructions
    in between. This is why this commit adds support for a wide range
    of integer instructions.

    Signed-off-by: Paul Mackerras

    Paul Mackerras