10 Jul, 2019
1 commit
01 Feb, 2019
1 commit
24 Jan, 2019
1 commit
31 Jan, 2018
1 commit
24 Jan, 2018
1 commit
11 Jan, 2018
1 commit
15 Sep, 2017
2 commits
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Add 900MHz/1.25V setpoint according the latest datasheet(Rev.1,2/2017),
we add a 25mV voltage margin to cover the IR frop and board tolerance.Signed-off-by: Bai Ping
(cherry picked from commit 9c31f7bf938adb9a808ea7bf637ccecf53f6e7be) -
According to the latest datasheet(Rev.1,02/2017), when the internal LDO
is enabled, the ARM core can run at 900MHz. We need to check the
speed grading fuse to determine the max ARM core frequency.Signed-off-by: Bai Ping
(cherry picked from commit cc0edd14c5fc3b5590302572687b08f80563c683)
05 Sep, 2017
1 commit
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The current code for deciding which CPU runs the complete lpi flow is
too complicated. Since all enter/exit code now runs under the same lock
we can just use a single non-atomic counter of cpus inside lpi.Another variable is used to make num_online_cpus() available to ASM code
but idle code can treat it as a constant.Signed-off-by: Leonard Crestez
30 Aug, 2017
1 commit
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The pcie dts node is dulicated, remove none-used one.
Signed-off-by: Richard Zhu
(cherry picked from commit c8b814b448d9ab3485d1f6c146da6dff03c63706)
29 Aug, 2017
1 commit
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Add focaltech new touch panel ft5246 support.
Set the ft5426 as default panel for dts. If want to use the old panel, then
it needs to boot with imx7ulp-evk-ft5416.dtb file.Signed-off-by: Fugang Duan
15 Aug, 2017
1 commit
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Add i2c bus recovery support to recover i2c2 bus from dead lock status.
Signed-off-by: Gao Pan
07 Aug, 2017
1 commit
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Update imx6ull header file with the latest imx6ull RDP.
- add new pin function definitions.
- update pin function changes.Signed-off-by: Fugang Duan
Reviewed-by: Richard Zhu
19 Jul, 2017
2 commits
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lcdif2 node has a property called "display" and a subnode that is also
called "display", leading to an OF duplicate warning at boot time.Fix this by changing the subnode's name to "display@1".
Signed-off-by: Cristina Ciocan
(cherry picked from commit 7aa2c6011a8a074b880330a7f3989ea9f23e03b3) -
This reverts commit d7d6f210522188 ("ARM: dts: imx6sx-sdb: Change audio
PLL frequency for SSI") because it breaks MQS.MQS uses IMX6SX_CLK_SAI1 as master clock and it requires mclk rate to be
24576000. No other rate is supported.Anyhow, due to change to fix MLK-14865 sai1 clk is changed to 36864000.
Signed-off-by: Daniel Baluta
18 Jul, 2017
1 commit
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Correct the CD pin for baseboard SD slot, otherwise
the card detection can't work.Signed-off-by: Haibo Chen
(cherry picked from commit 9869e681727490c3c23811a26bfc0e294cccd778)
07 Jul, 2017
1 commit
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This fixes commit 9982b452c61e ("MLK15034: ARM: cpuidle imx7d: Check
IPIs manually before LPI").Signed-off-by: Leonard Crestez
Reviewed-by: Anson Huang
06 Jul, 2017
3 commits
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Low power idle exit latency is much longer than declared, in the
milisecond range.Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez
Reviewed-by: Anson Huang -
The GPC will wake us on peripheral interrupts but not IPIs. So check
them manually by reading the GIC's GICD_SPENDSGIR* registers and
aborting idle if something is pending.We do this only for the last cpu and after taking the required locks.
We know that at this stage the other cpu is in WFI itself or waiting for
the imx_pen_lock and can't trigger any additional IPIs. This means that
the check is not racy.This fixes occasional lost IPIs causing tasks to get stuck in the
TASK_WAKING 'W' state for long periods. This eventually manifested as
rcu stalls.Signed-off-by: Leonard Crestez
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This makes the code much easier to reason about. In particular it o
makes sure the imx7d cpuidle driver respects the requirements for
cpu_cluster_pm_enter/exit:* cpu_cluster_pm_enter must be called after cpu_pm_enter has been called
on all cpus in the power domain, and before cpu_pm_exit has been called
on any cpu in the power domain.
* cpu_cluster_pm_exit must be called after cpu_pm_enter has been called
on all cpus in the power domain, and before cpu_pm_exit has been called
on any cpu in the power domain.This fixes interrupts sometimes getting "stuck" because of improper
save/restore of GIC DIST registers.Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez
Reviewed-by: Anson Huang
27 Jun, 2017
1 commit
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Default frequency is 786432000 and we cannot derive an exact bitclk
for 24 bits tests.This is similar with commit 9e3c04a3e9222a ("MLK-14781-2: ARM: dts: change
audio pll frequency for ssi master mode").Signed-off-by: Daniel Baluta
Reviewed-by: Shengjiu Wang
16 Jun, 2017
1 commit
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i.MX7ULP QSPI dtb was used to update the M4 images, it should not able
to boot the kernel even without the M4 image in QSPI.Also fixed the typo in dtsi to correct the QSPI register address
mapping range.Signed-off-by: Han Xu
(cherry picked from commit 6fb558d7e38a4f60944a791d4ff12fd5a5f039f5)
15 Jun, 2017
1 commit
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Update imx_v7_defconfig to match the output of 'make savedefconfig'.
Signed-off-by: Octavian Purdila
Reviewed-by: Anson Huang
14 Jun, 2017
2 commits
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IMX_SOC_IMX7 is referenced in makefiles and kconfig but it is not
defined, so define it and select it for both IMX7D and IMX7ULP.Fixes the following build errors:
arch/arm/mach-imx/built-in.o: In function `update_lpddr2_freq_smp':
platform-imx-dma.c:(.text+0xf7c): undefined reference to `imx_scu_base'
platform-imx-dma.c:(text+0xf88): undefined reference to `imx_scu_base'
arch/arm/mach-imx/built-in.o: In function `update_ddr_freq_imx_smp':
platform-imx-dma.c:(text+0x330c): undefined reference to `imx_scu_base'
platform-imx-dma.c:(text+0x3318): undefined reference to `imx_scu_base'
Makefile:969: recipe for target 'vmlinux' failed
make: *** [vmlinux] Error 1Signed-off-by: Octavian Purdila
Reviewed-by: Leonard Crestez -
The AIPSx address space of i.MX7ULP need to be mapped as SZ_1M block
in iRAM tlb for suspend code use. If we use ioremap to map these
address region into kernel space, we can't make sure that the returned
virtual address is 1M alignment. So we can map this address regions
as static, then if we use the ioremap to map these memory regions, it will
always return the virtual address of static mapping. So we can make sure
the virtual address is 1M aligned.Signed-off-by: Bai Ping
(cherry picked from commit 486041dc2fed38adc82ad93bd2dcc155c219ef01)
09 Jun, 2017
15 commits
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GPC will stop ARM clock if both CPUs are in idle and CPU_CLK_ON_LPM is
set in GPC_LPCR_A7_BSC. Make sure that doesn't happen when cpu1 enters
state2 and cpu0 enters state0 because the default arm WFI state is not
marked with CPUIDLE_FLAG_TIMER_STOP and it can result in arch_sys_timer
being stopped unexpectedly.It is possible to reproduce incorrect behavior by explicitly disabling
other idle states for cpu0/cpu1 and timing how much sleep calls take on
cpu0. Ocassionaly something like "sleep 1" will take 3-4 seconds to
complete.Make sure that both CPUs are in the same idle state before entering
WAIT.Signed-off-by: Leonard Crestez
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On most imx SOCs GPT1 takes it's clock from the oscillater because
otherwise it might get confusing when bus frequency is decreased.Right now imx7 is an exception because imx7s.dtsi comes from upstream
rather than a port of imx_4.1.y.On the imx_4.1.y branch imx7 uses GPT_3M as well, adopt that approach.
Signed-off-by: Leonard Crestez
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nand-on-flash-bbt flag for i.mx6sx sabreauto dtb was set in wrong device
node, move it back to gpmi node.Signed-off-by: Han Xu
(cherry picked from commit 07643110a47b5c1982057e77316f229fa66740b5) -
Remove usless 'fsl,wdog-reset' property in dts on v4.9
Signed-off-by: Robin Gong
(cherry picked from commit bfe33c0df6a7cba546fcc5b30609be277f499af2) -
align watchdog external reset output property with community
instead of "fsl,wdog_b".Signed-off-by: Robin Gong
(cherry picked from commit c07391d10d74a1c85a0978085a3ac0a761fb6410) -
Default compile the usdhc driver into kernel
Signed-off-by: Haibo Chen
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Fix the same issue as commit bf23e0c5ea31 on imx6qp-saresd-hdcp board
Signed-off-by: Robin Gong
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Fix below pfuze probe issue by setting correct range of SW3B:
pfuze100-regulator 0-0008: pfuze200 found.
SW3B: Bringing 3300000uV into 1975000-1975000uV
SW3B: failed to apply 1975000-1975000uV constraint(-22)
pfuze100-regulator 0-0008: register regulatorSW3B failed
pfuze100-regulator: probe of 0-0008 failed with error -22
2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 19, base_baud = 5000000) is a IMXSigned-off-by: Anson Huang
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Add USB OTG1 port ID pin for imx6ul-14x14-evk.dts
Acked-by: Peter Chen
Signed-off-by: Li Jun -
Add USB OTG1 port ID pin for imx6ull-14x14-evk.dts
Acked-by: Peter Chen
Signed-off-by: Li Jun -
Correct CD/WP pin in dts. Otherwise the card detection and write
protection function does not work.Signed-off-by: Dong Aisheng
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According to RM, Bit[11-8] is MUX_MODE which is configured by
the PIN_FUNC_ID automatically, specify it in config part is wrong
and violates the binding doc. So remove them all.It can also avoid the future confusing when customer wants to
configure a pad by following the exist code.Signed-off-by: Dong Aisheng
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Add i.MX7ULP binding doc. Note i.MX7ULP PIN_FUNC_ID consists of 4
integers as it shares one mux and config register as follows:Also fix the copyright.
Signed-off-by: Dong Aisheng
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'vin-supply' property used in ldo-bypass mode while 'vin-supply' deleted
in ldo-enable mode on v4.9 rather than dirctly switch 'supply' to internal
regulator and external pmic regulator on v4.1. Correct it for all *-ldo.dts,
otherwise, still work in ldo-bypass mode.Signed-off-by: Robin Gong
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I2C2 have to be disabled on hdcp board since those I2C2 bus pins
used for others, that said there is no all pmic regulators. In this
case, ldo-enable mode should be used and reg_arm/reg_soc/reg_pu should
be swithed to internal ldo instead. Otherwise, no reg_pu regulator
probed successfully by gpu driver, and cause gpu probe failed. Also,
cause cpufreq probe failed too.Signed-off-by: Robin Gong
