Eric Lee / smarc-fsl-linux-kernel

17 Sep, 2015

1 commit

  • 2110d70c5   cpu/cacheinfo: Fix teardown path ... Browse Code »

    Philip Müller reported a hang when booting 32-bit 4.1 kernel on an AMD
    box. A fragment of the splat was enough to pinpoint the issue:

    task: f58e0000 ti: f58e8000 task.ti: f58e800
    EIP: 0060:[] EFLAGS: 00010206 CPU: 0
    EIP is at free_cache_attributes+0x83/0xd0
    EAX: 00000001 EBX: f589d46c ECX: 00000090 EDX: 360c2000
    ESI: 00000000 EDI: c1724a80 EBP: f58e9ec0 ESP: f58e9ea0
    DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
    CR0: 8005003b CR2: 000000ac CR3: 01731000 CR4: 000006d0

    cache_shared_cpu_map_setup() did check sibling CPUs cacheinfo descriptor
    while the respective teardown path cache_shared_cpu_map_remove() didn't.
    Fix that.

    >From tglx's version: to be on the safe side, move the cacheinfo
    descriptor check to free_cache_attributes(), thus cleaning up the
    hotplug path a little and making this even more robust.

    Reported-and-tested-by: Philip Müller
    Reviewed-by: Thomas Gleixner
    Acked-by: Sudeep Holla
    Cc: # 4.1
    Cc: Andre Przywara
    Cc: Guenter Roeck
    Cc: "H. Peter Anvin"
    Cc: Ingo Molnar
    Cc: linux-kernel@vger.kernel.org
    Cc: manjaro-dev@manjaro.org
    Cc: Philip Müller
    Link: https://lkml.kernel.org/r/55B47BB8.6080202@manjaro.org
    Signed-off-by: Borislav Petkov
    Signed-off-by: Greg Kroah-Hartman

    Borislav Petkov
     

09 Jun, 2015

1 commit

01 Jun, 2015

1 commit

  • 3370e13aa   drivers/base: cacheinfo: handle absence of caches ... Browse Code »

    On some simulators like GEM5, caches may not be simulated. In those
    cases, the cache levels and leaves will be zero and will result in
    following exception:

    Unable to handle kernel NULL pointer dereference at virtual address 0040
    pgd = ffffffc0008fa000
    [00000040] *pgd=00000009f6807003, *pud=00000009f6807003,
    *pmd=00000009f6808003, *pte=006000002c010707
    Internal error: Oops: 96000005 [#1] PREEMPT SMP
    Modules linked in:
    CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.1.0-rc5 #198
    task: ffffffc9768a0000 ti: ffffffc9768a8000 task.ti: ffffffc9768a8000
    PC is at detect_cache_attributes+0x98/0x2c8
    LR is at detect_cache_attributes+0x88/0x2c8

    kcalloc(0) returns a special value ZERO_SIZE_PTR which is non-NULL value
    but results in fault only on any attempt to dereferencing it. So
    checking for the non-NULL pointer will not suffice.

    This patch checks for non-zero cache leaf nodes and returns error if
    there are no cache leaves in detect_cache_attributes.

    Cc: # 3.19.x
    Cc: Will Deacon
    Cc: Greg Kroah-Hartman
    Reported-by: William Wang
    Signed-off-by: Sudeep Holla
    Signed-off-by: Greg Kroah-Hartman

    Sudeep Holla
     

25 May, 2015

1 commit

25 Mar, 2015

1 commit

  • 8a7d95f95   drivers/base: cacheinfo: validate device node for all the caches ... Browse Code »

    On architectures that depend on DT for obtaining cache hierarcy, we need
    to validate the device node for all the cache indices, failing to do so
    might result in wrong information being exposed to the userspace.

    This is quite possible on initial/incomplete versions of the device
    trees. In such cases, it's better to bail out if all the required device
    nodes are not present.

    This patch adds checks for the validation of device node for all the
    caches and doesn't initialise the cacheinfo if there's any error.

    Reported-by: Mark Rutland
    Acked-by: Mark Rutland
    Signed-off-by: Sudeep Holla
    Cc: stable # 4.0
    Signed-off-by: Greg Kroah-Hartman

    Sudeep Holla
     

25 Nov, 2014

1 commit

  • 6df43c9b4   drivers/base: cacheinfo: remove noisy error boot message ... Browse Code »

    On systems that don't support cacheinfo, this error message can be
    considered noisy and irrelevant. The error messages can be added to
    the functions that architectures implement overiding the weak default
    definition if really required.

    This patch removes the concerned error message in the generic code.

    Signed-off-by: Sudeep Holla
    Reported-by: Fabio Estevam
    Signed-off-by: Greg Kroah-Hartman

    Sudeep Holla
     

08 Nov, 2014

1 commit

  • 246246cbd   drivers: base: support cpu cache information interface to userspace via sysfs ... Browse Code »

    This patch adds initial support for providing processor cache information
    to userspace through sysfs interface. This is based on already existing
    implementations(x86, ia64, s390 and powerpc) and hence the interface is
    intended to be fully compatible.

    The main purpose of this generic support is to avoid further code
    duplication to support new architectures and also to unify all the existing
    different implementations.

    This implementation maintains the hierarchy of cache objects which reflects
    the system's cache topology. Cache devices are instantiated as needed as
    CPUs come online. The cache information is replicated per-cpu even if they are
    shared. A per-cpu array of cache information maintained is used mainly for
    sysfs-related book keeping.

    It also implements the shared_cpu_map attribute, which is essential for
    enabling both kernel and user-space to discover the system's overall cache
    topology.

    This patch also add the missing ABI documentation for the cacheinfo sysfs
    interface already, which is well defined and widely used.

    Signed-off-by: Sudeep Holla
    Reviewed-by: Stephen Boyd
    Tested-by: Stephen Boyd
    Cc: Greg Kroah-Hartman
    Cc: linux-api@vger.kernel.org
    Cc: linux390@de.ibm.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-ia64@vger.kernel.org
    Cc: linuxppc-dev@lists.ozlabs.org
    Cc: linux-s390@vger.kernel.org
    Cc: x86@kernel.org
    Signed-off-by: Greg Kroah-Hartman

    Sudeep Holla