07 Mar, 2016
1 commit
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This follows the way of handling other flashes and cleans code a bit. As
next task we will want to move flash code to ChipCommon driver as:
1) Flash controllers are accesible using ChipCommon registers
2) This code isn't MIPS specific
This change prepares bcma for that.Signed-off-by: Rafał Miłecki
Signed-off-by: Kalle Valo
05 Mar, 2015
1 commit
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Driver for PCIe core requires PCI to be enabled, however we shouldn't
require it for the whole bus. Someone may be not interested in extra
PCI devices and what's more there are SoCs without any PCI at all (like
BCM5356C0, BCM5357*, BCM47186B0). For more details see Kconfig "help".
Please note this patch doesn't allow disabling PCI drivers yet, as it
requires more work on calls to bcma_core_pci_* functions.Signed-off-by: Rafał Miłecki
Signed-off-by: Kalle Valo
10 Sep, 2014
1 commit
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This core is used on BCM4708 to configure the PCIe and USB3 PHYs and it
contains the addresses to the Device Management unit. This will be used
by the PCIe driver first.Signed-off-by: Hauke Mehrtens
Signed-off-by: John W. Linville
08 Jul, 2014
1 commit
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New Broadcom PCIe devices (802.11ac ones?) use Gen2 and have to be
initialized differently.Signed-off-by: Rafał Miłecki
Signed-off-by: John W. Linville
22 Nov, 2012
1 commit
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Register a GPIO driver to access the GPIOs provided by the chip.
The GPIOs of the SoC should always start at 0 and the other GPIOs could
start at a random position. There is just one SoC in a system and when
they start at 0 the number is predictable.Signed-off-by: Hauke Mehrtens
Patchwork: http://patchwork.linux-mips.org/patch/4587
Acked-by: Florian Fainelli
18 Jul, 2012
1 commit
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Signed-off-by: Rafał Miłecki
Signed-off-by: John W. Linville
13 Jul, 2012
1 commit
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GMAC COMMON core is present on BCM4706 and is used for example to access
board PHYs (PHYs can not be accessed directly using GBIT MAC core).Signed-off-by: Rafał Miłecki
Acked-by: Hauke Mehrtens
Signed-off-by: John W. Linville
09 Aug, 2011
2 commits
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This adds a mips driver to bcma. This is only found on embedded
devices. For now the driver just initializes the irqs used on this
system.Signed-off-by: Hauke Mehrtens
Acked-by: Ralf Baechle
Signed-off-by: John W. Linville -
This patch adds support for using bcma on a Broadcom SoC as the system
bus. An SoC like the bcm4716 could register this bus and use it to
searches for the bcma cores and register the devices on this bus.BCMA_HOSTTYPE_NONE was intended for SoCs at first but BCMA_HOSTTYPE_SOC
is a better name.Acked-by: Rafał Miłecki
Signed-off-by: Hauke Mehrtens
Acked-by: Ralf Baechle
Signed-off-by: John W. Linville
08 Jul, 2011
1 commit
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We must not init it like clientmode one, it would break device (tested
by Hauke on BCM4718). Add stub hostmode driver for now.Signed-off-by: Rafał Miłecki
Signed-off-by: Hauke Mehrtens
Signed-off-by: John W. Linville
04 Jun, 2011
1 commit
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In case of BCMA cards SPROM is located in the ChipCommon core, it is
not mapped as separated host window. So far we have met only SPROMs rev
8.
SPROM layout seems to be the same as for SSB buses, so we decided to
share SPROM struct and some defines.
For now we extract MAC address only, this can be improved of course.Signed-off-by: Rafał Miłecki
Signed-off-by: John W. Linville
11 May, 2011
1 commit
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Broadcom has released cards based on a new AMBA-based bus type. From a
programming point of view, this new bus type differs from AMBA and does
not use AMBA common registers. It also differs enough from SSB. We
decided that a new bus driver is needed to keep the code clean.In its current form, the driver detects devices present on the bus and
registers them in the system. It allows registering BCMA drivers for
specified bus devices and provides them basic operations. The bus driver
itself includes two important bus managing drivers: ChipCommon core
driver and PCI(c) core driver. They are early used to allow correct
initialization.Currently code is limited to supporting buses on PCI(e) devices, however
the driver is designed to be used also on other hosts. The host
abstraction layer is implemented and already used for PCI(e).Support for PCI(e) hosts is working and seems to be stable (access to
80211 core was tested successfully on a few devices). We can still
optimize it by using some fixed windows, but this can be done later
without affecting any external code. Windows are just ranges in MMIO
used for accessing cores on the bus.Cc: Greg KH
Cc: Michael Büsch
Cc: Larry Finger
Cc: George Kashperko
Cc: Arend van Spriel
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King
Cc: Arnd Bergmann
Cc: Andy Botting
Cc: linuxdriverproject
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Rafał Miłecki
Signed-off-by: John W. Linville