11 Jan, 2018
1 commit
20 Jun, 2017
1 commit
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The clock driver may enable uart clock tree when earlycon/earlyprintk
kernel param is enabled, and the clock gate specify CLK_SET_RATE_GATE,
then .of_clk_set_defaults() set the dts node assigned-rate will be failed.
So set parent and set rate in clock driver is reasonable.Signed-off-by: Fugang Duan
09 Jun, 2017
8 commits
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According to design, PFD needs to be gated before
setting rate, this patch adds warning for PFD when
there is any try to set PFD rate with gate open;Since PFD may be enabled during kernel boot up,
here doing enable and disable before setting APLL_PFD2
rate is to make sure it is gated by clock framework
before setting rate.Signed-off-by: Anson Huang
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Signed-off-by: Irina Tirdea
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In upstream, IMX7D_ARM_A7_ROOT_SRC uses imx_clk_mux2 for initialization,
while our code uses imx_clk_mux_flags_bus with additional flags
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE. In the end, both calls
set the flags of IMX7D_ARM_A7_ROOT_SRC clock to
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE.To align our code to upstream, we can safely use imx_clk_mux2.
Signed-off-by: Irina Tirdea
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Update imx7d clk platform code according to upstream commit
40e00ef ("clk: imx7d: add the missing ipg_root_clk").Signed-off-by: Irina Tirdea
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Fixed the clock rate to 350M Hz to meet the design.
Signed-off-by: Yuchou Gan
Date: 13 April, 2017 -
spdif clock is one of the asrc clock source, which is used
for ideal ratio mode. when set to 98.304MHz, it cause the
divider of asrc input clock and output clock exceed the
maximum value, and asrc driver saturate the value to maximum
value, which will cause the ASRC's performance very bad.
So we need to set spdif clock to a proper rate. which make asrc
divider not exceed maximum value, at least one of divider not
exceed maximum value.
The target is spdif clock rate / output(or input) sample rate
less than 1024(which is maximum divider).Signed-off-by: Shengjiu Wang
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The mpll can only be configured by mipi dphy and it is disabled
by default. And it is also not a fixed frequency clock source.
So replace it with a dummy clock for 'periph_slow_sels' to avoid
any peripheral except mipi to use it for clock source.Signed-off-by: Fancy Fang
(cherry picked from commit a7c6555e0d79491b939b84af99969b21264ec9f8)Conflicts:
arch/arm/mach-imx/clk-imx7ulp.c -
Currently, it is failed to set clock rate in dts file that maybe some clock
patch miss. Now just set the clock parent and rate in clock driver.Signed-off-by: Fugang Duan
08 Jun, 2017
30 commits
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This fixes crashing on boot on imx7d if imx_src_is_m4_enabled(). This
check was lost when porting 24ee04ce76d6a8d8229c642eb5d7a15ea57570c6.Signed-off-by: Leonard Crestez
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Fix IPU2 DI(Display Interface) clocks for iMX6QP SABRESD. The upstream
version uses ldb_di0_podf and ldb_di1_podf as clock parents for ipu_di,
which fails to work on iMX6QP SABRESD. This patch fixes clock tree by:
- setting ipu_di selectors to ldb_di_div_sel in imx6q clock driver
- matching "ldb_di0", "ldb_di1" clock names with
IMX6QDL_CLK_LDB_DI0_DIV_SEL, IMX6QDL_CLK_LDB_DI1_DIV_SEL; otherwise,
ldb_di0_div_sel and ldb_di1_div_sel will not be recognized as LDB clk parents
and will not drive the Display Interface.Signed-off-by: Cristina Ciocan
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Add HSRUN mode clocks on i.MX7ULP. we also add a fake clock mux ARM
to make the clock tree more easy to handle in cpufreq.Signed-off-by: Bai Ping
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Add gpt_3m clock source on i.MX6SLL.
Signed-off-by: Bai Ping
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Correct enet clock CCGR register offset.
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLKIMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
clcok root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
no gate after the clock, its parent clock root has gate.IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.
Update copyright information.
Signed-off-by: Fugang Duan
Signed-off-by: Adrian Alonso -
Using the CLK_GET_RATE_NOCACHE flag on the clock dividers will allow
the recalculation of the rate instead of just caching its value.For instance, this allows the mmdc clock to be properly updated,
after being modified by the busfreq driver, within an iram routine
by calling the clk_get_rate api. Using this flag allows to call only
to the .recalc_rate functions instead of additionally call the
.set_rate ones.Signed-off-by: Juan Gutierrez
Signed-off-by: Ranjani Vaidyanathan -
Do not enable the gpu clock when initialize the clock
Date: Dec 30, 2016
Signed-off-by: Yuchou Gan -
Workaround for ERR010579
When switching the clock source of IPU clock root in CCM, even setting
CCGR3[CG0]=0x0 to gate off clock before switching, IPU may hang due to
no IPU clock from CCM. The root cause is an integration bug in SOC level,
setting CCGR3[CG0]=0x0 can NOT gate off the clock after IPU clock source MUX.The IPU clock source MUX is glitchg MUX, that means the clock glitch during
clock switch is unavoidable, which will cause the divider after it stop work
and no clock output. In order to avoid the clock glitch, we must obey below
procedures if clock source switch is needed:1. gate off the CG after MUX
2. switch clock source
3. gate on the CG after MUXOn the other hand, the EN of the CG between MUX and divider is a feedback
logic(OR result) from several LPCG cells in SOC top, but for IPU clock, one
LPCG is forced to open forever, then the feedback OR result is always high,
it causes the CG can NOT be gated off even the CCGR3[CG0] is set to 0x0.For detailed workaround steps, please refer to the errata document.
Tested-by: Ying Liu
Signed-off-by: Bai Ping -
This reverts commit 322503a15740bd9383bb4ed452e5dd5a40598170.
The driver for clk-pllv3 has moved from arch/arm/mach-imx/clk-pllv3.c
to drivers/clk/imx/clk-pllv3.c since the orginal change was made,
so the revert is done to the new file instead.Signed-off-by: Irina Tirdea
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The nand_usdhc_root_clk and ahb_root_clk clocks need to be initialized
earlier so the board can boot, since there are other clocks that
depend on them.This is a leftover from rebasing patch a06eafc305c4c2db6dfc3de372f667af0135fa9e
(MLK-11349-3 ARM: imx: update clk driver for imx7d), that has the clocks
initialized in the correct order.Signed-off-by: Irina Tirdea
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Increase the gpu 2d and 3d frequency to 475M Hz on 7ULP
Signed-off-by: Yuchou Gan
Date: Dec 20, 2016 -
This patch fixes below build warning:
CC arch/arm/mach-imx/clk-imx7ulp.o
LD init/built-in.o
arch/arm/mach-imx/clk-imx7ulp.c:42:20: warning: 'cm4_periph_plat_sels' defined but not used [-Wunused-variable]
LD arch/arm/mach-imx/built-in.o
CC kernel/module.o
GZIP kernel/config_data.gzSigned-off-by: Anson Huang
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SAI in M4 domain, and the clock used by SAI is in M4 domain
Signed-off-by: Shengjiu Wang
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Add gpio port control clocks, and add them to init table.
If the gpio clock is controlled by gpio driver, the watchdog
reset will occur due to unknown reason, we need to debug it
if we need driver to control its clocks.Signed-off-by: Peter Chen
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Improve the fractional divider calculation accuracy use
continued fraction method.Signed-off-by: Bai Ping
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On i.MX7ULP, there are options to select SPLL or SPLL PFD
as SPLL output clock SPLL_SEL, so the SPLL option for
sys_sel mux should be from SPLL_SEL, NOT from SPLL directly.Previous:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 2 2 531648000 0
sys_sel 1 1 531648000 0
core_div 2 2 531648000 0
plat_div 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 1 1 503666526 0
spll_pfd_sel 0 0 503666526 0
spll_sel 0 0 503666526 0
After fixed:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 2 2 503666526 0
spll_pfd_sel 1 1 503666526 0
spll_sel 1 1 503666526 0
sys_sel 1 1 503666526 0
core_div 1 1 503666526 0
plat_div 1 1 503666526 0CORE_DIV clock will be enabled automatically when PLAT_DIV
is enabled, so we can skip it in clks_init_on.Now that sys_sel clock tree is correct, no need to have SPLL_PFD0
in clks_init_on, as it will be enabled automatically because of
PLAT_DIV.Signed-off-by: Anson Huang
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change parent clock to pll3_pfd2 and calculate out a desired pixel clock
rate. This patch fixed the following warning.
"imx_epdc_v2_fb 20f4000.epdc: Unable to get an accurate EPDC pix clkdesired = 40000000, actual = 63529412"Signed-off-by: Robby Cai
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When enter VLLS mode, DRAM is in self-refresh, NVCC_DRAM_SW
can be off to save power.As the static io-map formula is no longer feasible on i.MX7ULP,
here we change it to ioremap for creating iram tlb.Remove the physical module base address in pm_info structure
to save iram space.Signed-off-by: Anson Huang
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The PCC clock bit field definition is as below:
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5So previous clock driver sets PCC clock parent to
start from index value 1 by setting CLK_MUX_INDEX_ONE
flag, however it has an issue of getting clock parent
when the register field value is 0, below is the clk
get parent code from clk driver:if (val && (mux->flags & CLK_MUX_INDEX_BIT))
val = ffs(val) - 1;if (val && (mux->flags & CLK_MUX_INDEX_ONE))
val--;The val is 0, so the parent will be returned as first
clock parent in PCC register field which is 001b,
that will cause setting clk parent fail when the
reset value is 0 and we try to set clk parent to
option 1, as clk driver thinks current clk parent
is same as the new parent.Fix this issue by adding dummy clock as option0, ths
clk gate is controlled by bit 30, so it would NOT impact
gating function.Signed-off-by: Anson Huang
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Add i.MX7ULP clock driver.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Fancy Fang -
Add below new clock types to support new SoC:
composite clk;
frac-divider;
pfdv2;
pllv4.These clock types are for i.MX7ULP and maybe
following SoCs.Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
[Octavian: fix build warning by using u64 in do_div ops]
Signed-off-by: Octavian Purdila -
Increase the AXI and AHB clock rate on i.MX6SLL according to
the RM to improve the system bus performance.Signed-off-by: Bai Ping
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add extern audio clock in imx6sll clock tree
Signed-off-by: Shengjiu Wang
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Add clock driver for i.MX6SLL.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Frank Li -
When the external oscillator is used as pcie ref clk.
the below configurations should done.
- set the lvds_clk1 as input
- set the source of the pll6_bypass to be lvds_clk1
- set the pll6 to be bypass mode.Signed-off-by: Richard Zhu
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When i.MX6QP with speed grading fuse blown to 1.2GHz,
VPU should run at 396MHz, add this support.Signed-off-by: Anson Huang
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On i,MX6SL, no NUM and DENUM register, so this PLL should not
be registered as IMX_PLLV3_GENERIC type PLL, it should be
registered as IMX_PLLV3_SYSV2.Signed-off-by: Bai Ping
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As i.MX6's PLL2 also support a fractional-N
synthesizer, so we need to consider the NUM
and DENOM's value to get a correct rate, as
fraction may be used in some cases.Remove round_rate and set_rate for PLL2, as
it is NOT allowed to be changed in kernel
dynamically, otherwise, PFDs and DDR may NOT
work normally, it normally should be changed
in u-boot before DDR is enabled.Signed-off-by: Anson Huang
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i.MX6SX LDB will connect to LCDIF2.
And LCDIF2 pixel clock can not re-parent when it's on.
So default setting clock parent to ldb_di0.Signed-off-by: Sandor Yu
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For i.MX7D, current runtime clock management code will skip all
PLL/PFD/GATE enable/disable when M4 is enabled, this is NOT good
for power number in low power idle and audio playback, as M4 only
uses one high speed PFD which is from system PLL, it is never
disabled runtimely, so we can just enable the hardware operation of
PLL/PFD/GATE for A7.Signed-off-by: Anson Huang
(cherry picked from commit 02a2e8d73bcb8d2b8362b4328976dfcdc502a19c)
