08 Oct, 2016
1 commit
-
Pull ARM SoC cleanups from Arnd Bergmann:
"The cleanups for v4.9 are a little larger that usual, but thankfully
that is almost exclusively due to removing a significant number of
files that have become obsolete after the still ongoing conversion of
old board files to devicetree.- for mach-omap2, which is still the largest platform in arch/arm/,
the conversion to DT is finally complete after the Nokia N900 is
now fully supported there, along with the omap3 LDP, and we can
remove those two board files. If no regressions are found, another
large cleanup for the platform will happen as a follow-up, removing
dead code and restructuring the platform based on being DT-only.- In mach-imx, similar work is ongoing, but has not come that far.
This time, we remove the obsolete board file for the i.MX1
generation, which like i.MX25, i.MX5, i.MX6, and i.MX7 is now
DT-only. The remaining board files are for i.MX2 and i.MX3 machines
based on old ARM926 or ARM1136 cores that should work with DT in
principle.- realview has just been converted from board files to DT, and a lot
of code gets removed in the process. This is the last
ARM/Keil/Versatile derived platform that was still using board
files, the other ones being integrator, versatile and vexpress. We
can probably merge the remaining code into a single directory in
the near future.- clps711x had completed the conversion in v4.8, but we accidentally
left the files in place that should have been deleted then"* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits)
ARM: select PCI_DOMAINS config from ARCH_MULTIPLATFORM
ARM: stop *MIGHT_HAVE_PCI* config from being selected redundantly
ARM: imx: (trivial) fix typo and grammar
ARM: clps711x: remove extraneous files
ARM: imx: use IS_ENABLED() instead of checking for built-in or module
ARM: OMAP2+: use IS_ENABLED() instead of checking for built-in or module
ARM: OMAP1: use IS_ENABLED() instead of checking for built-in or module
ARM: imx: remove platform-mxc_rnga
ARM: realview: imply device tree boot
ARM: realview: no need to select SMP_ON_UP explicitly
ARM: realview: delete the RealView board files
ARM: imx: no need to select SMP_ON_UP explicitly
ARM: i.MX: Move SOC_IMX1 into 'Device tree only'
ARM: i.MX: Remove i.MX1 non-DT support
ARM: i.MX: Remove i.MX1 Synertronixx SCB9328 board support
ARM: i.MX: Remove i.MX1 Armadeus APF9328 board support
ARM: mxs: remove obsolete startup code for TX28
ARM: i.MX31 iomux: remove duplicates with alternate name
ARM: i.MX31 iomux: remove plain duplicates
ARM: OMAP2+: Drop legacy board file for LDP
...
23 Sep, 2016
1 commit
-
Pull irqchip core changes for v4.9 from Jason Cooper
- jcore: Add AIC driver
- mips-gic: Use for_each_set_bit
- mvebu: Add PIC driver
21 Sep, 2016
1 commit
-
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.Originally-from: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
Cc: Mark Rutland
Cc: devicetree@vger.kernel.org
Cc: Daniel Thompson
Cc: Jason Cooper
Cc: arnd@arndb.de
Cc: Marc Zyngier
Cc: bruherrera@gmail.com
Cc: Linus Walleij
Cc: linux-gpio@vger.kernel.org
Cc: Rob Herring
Cc: lee.jones@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1474387259-18926-3-git-send-email-alexandre.torgue@st.com
Signed-off-by: Thomas Gleixner
23 Aug, 2016
2 commits
-
The Marvell Armada 7K/8K integrates a secondary interrupt controller
very originally named "PIC". It is connected to the main GIC via a
PPI. Amongst other things, this PIC is used for the ARM PMU.This commit adds a simple irqchip driver for this interrupt
controller. Since this interrupt controller is not needed early at boot
time, we make the driver a proper platform driver rather than use the
IRQCHIP_DECLARE() mechanism.Signed-off-by: Yehuda Yitschak
Signed-off-by: Thomas Petazzoni
Link: https://lkml.kernel.org/r/1470408921-447-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper
16 Aug, 2016
1 commit
-
This reduces the Kconfig for the RealView by assuming we are
always booting from the device tree, and removing all the uses
of CONFIG_REALVIEW_DT and replacing with CONFIG_ARCH_REALVIEW.Further:
- Drop REALVIEW_HIGH_PHYS_OFFSET: we don't use this with device
tree.- Drop the REALVIEW_EB_ARM11MP_REVB option: we now handle this
by simply using another device tree.- Drop the PB1176 secure flash option: this is defined in the
PB1176 device tree but marked as "disabled", so users who
want to use it can simply enable it in the device tree and
go hacking around.Cc: Brian Norris
Cc: Marc Zyngier
Cc: Thomas Gleixner
Signed-off-by: Linus Walleij
09 Aug, 2016
1 commit
-
There are two versions of the J-Core interrupt controller in use, aic1
which generates interrupts with programmable priorities, but only
supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
and aic2 which uses traps in the range 64-127 and supports up to 128
irqs, with priorities dependent on the interrupt number. The Linux
driver does not make use of priorities anyway.For simplicity, there is no aic1-specific logic in the driver beyond
setting the priority register, which is necessary for interrupts to
work at all. Eventually aic1 will likely be phased out, but it's
currently in use in deployments and all released bitstream binaries.Signed-off-by: Rich Felker
Link: https://lkml.kernel.org/r/c3b89ef74aaa6477575dbe2d410eb1d182503243.147018b6529.git.dalias@libc.org
Signed-off-by: Jason Cooper
02 Jul, 2016
1 commit
-
Pull irqchip core changes for v4.8 (second set) from Jason Cooper:
- Add Aspeed VIC driver
23 Jun, 2016
1 commit
-
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Joel Stanley
Link: https://lkml.kernel.org/r/1463064193-2178-3-git-send-email-joel@jms.id.au
Signed-off-by: Jason Cooper
13 Jun, 2016
1 commit
-
Add a platform driver to support non-root GICs that require runtime
power-management. Currently, only non-root GICs are supported because
the functions, smp_cross_call() and set_handle_irq(), that need to
be called for a root controller are located in the __init section and
so cannot be called by the platform driver.The GIC platform driver re-uses many functions from the existing GIC
driver including some functions to save and restore the GIC context
during power transitions. The functions for saving and restoring the
GIC context are currently only defined if CONFIG_CPU_PM is enabled and
to ensure that these functions are always defined when the platform
driver is enabled, a dependency on CONFIG_ARM_GIC_PM (which selects the
platform driver) has been added.In order to re-use the private GIC initialisation code, a new public
function, gic_of_init_child(), has been added which calls various
private functions to initialise the GIC. This is different from the
existing gic_of_init() because it only supports non-root GICs (ie. does
not call smp_cross_call() is set_handle_irq()) and is not located in
the __init section (so can be used by platform drivers). Furthermore,
gic_of_init_child() dynamically allocates memory for the GIC chip data
which is also different from gic_of_init().There is no specific suspend handling for GICs registered as platform
devices. Non-wakeup interrupts will be disabled by the kernel during
late suspend, however, this alone will not power down the GIC if
interrupts have been requested and not freed. Therefore, requestors of
non-wakeup interrupts will need to free them on entering suspend in
order to power-down the GIC.Signed-off-by: Jon Hunter
Signed-off-by: Marc Zyngier
20 May, 2016
1 commit
-
Pull ARC updates from Vineet Gupta:
"We have a relatively big changeset for ARC for 4.7.The highlight is support for EZChip (now Mellanox) NPS-400 network
processor, a 400-Gb throughput C-programmable packet processor based
on ARC700 cores from Synopsys. Seehttp://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf
Also present are irqchip and clocksource drivers for NPS as agreed
with respective maintainers to go via ARC tree due to an soc header
dependency. I have the needed ACKs from Jason, Marc, Daniel. You
might run into a trivial merge conflict in drivers/irqchip/*This EZChip platform support required some deep changes in ARC
architecture code and also opportunity to cleanup past sins (legacy
irq domains, missing irq domain lookup, hard coded timer irqs...)Summary:
- Support for EZChip (now Mellanox) NPS-400 Network processor based
on ARC700- NPS interrupt controller and clocksource drivers
- ARC timers probed off DT
- ARC iqrchips switching to linear domain (upgrade from legacy
domains)"* tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (37 commits)
arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core
arc: axs10x: Add DT bindings for I2S PLL Clock
ARC: pae: STRICT_MM_TYPECHECKS was broken
ARC: Add eznps platform to Kconfig and Makefile
ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
ARC: [plat-eznps] Use dedicated cpu_relax()
ARC: [plat-eznps] Use dedicated identity auxiliary register.
ARC: [plat-eznps] Use dedicated SMP barriers
ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
ARC: [plat-eznps] Use dedicated user stack top
ARC: [plat-eznps] Add eznps platform
ARC: [plat-eznps] Add eznps board defconfig and dts
ARC: Mark secondary cpu online only after all HW setup is done
ARC: rwlock: disable interrupts in !LLSC variant
ARC: Make vmalloc size configurable
ARC: clean out UAPI byteorder.h clean off Kconfig symbol
irqchip: add nps Internal and external irqchips
clocksource: Add NPS400 timers driver
soc: Support for EZchip SoC
Documentation: Add EZchip vendor to binding list
...
11 May, 2016
1 commit
-
The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
interrupt controllers.This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to
hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems
with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle
them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register
offsets,
* the driver is much simpler for maintenance,
* SPARSE_IRQS option is supported.Legacy LPC32xx interrupt controller driver was broken since commit
76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
requires a private interrupt handler, otherwise any SIC1 generated
interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
"unexpected IRQ trap at vector 00".The change disables compilation of a legacy driver found at
arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
commit.Fixes: 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler")
Tested-by: Sylvain Lemieux
Signed-off-by: Vladimir Zapolskiy
Signed-off-by: Marc Zyngier
09 May, 2016
1 commit
-
Adding EZchip NPS400 support.
Internal interrupts are handled by Multi Thread Manager (MTM)
Once interrupt is serviced MTM is acked for deactivating the interrupt.
External interrupts are handled by MTM as well as at Global Interrupt
Controller (GIC) e.g. serial and network devices.Signed-off-by: Noam Camus
Acked-by: Marc Zyngier
Acked-by: Vineet Gupta
Acked-by: Jason Cooper
Cc: Thomas Gleixner
04 May, 2016
1 commit
-
Some kind of Freescale Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.Signed-off-by: Minghuan Lian
Tested-by: Alexander Stein
Acked-by: Marc Zyngier
Signed-off-by: Marc Zyngier
02 May, 2016
1 commit
-
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.Signed-off-by: Marc Zyngier
Cc: Mark Rutland
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper
Cc: Will Deacon
Cc: Rob Herring
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
09 Mar, 2016
1 commit
-
This patch adds the Alpine MSIX interrupt controller driver.
Signed-off-by: Antoine Tenart
Signed-off-by: Tsahee Zidenberg
Acked-by: Marc Zyngier
Signed-off-by: Marc Zyngier
22 Feb, 2016
2 commits
-
Pull the second round of irqchip core changes for v4.6 from Jason Cooper:
- mvebu:
- Add odmi driver for Marvell 7K/8K SoCs
- Replace driver-specific set_affinity with generic version- mips:
- Move ath79 MISC and CPU drivers from arch/ code to irqchip/- tango:
- Add support for Sigma Designs SMP8[67]xx ctrl -
Pull irqchip core changes for v4.6 from Jason Cooper:
- mvebu (armada-370-xp)
- MSI support
- Deconflict with mvebu's arm64 code- ts4800
- Restrict when ts4800 driver can be built
- Make ts4800_ic_ops static const- bcm2836: Drop superfluous memory barrier
21 Feb, 2016
3 commits
19 Feb, 2016
1 commit
-
This commits adds a new irqchip driver that handles the ODMI
controller found on Marvell 7K/8K processors. The ODMI controller
provide MSI interrupt functionality to on-board peripherals, much like
the GIC-v2m.Signed-off-by: Thomas Petazzoni
Reviewed-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper
18 Feb, 2016
1 commit
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This adds support for the secondary interrupt controller used in Sigma
Designs SMP86xx and SMP87xx chips.Signed-off-by: Mans Rullgard
Acked-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1453313237-18570-2-git-send-email-mans@mansr.com
Signed-off-by: Jason Cooper
17 Feb, 2016
3 commits
-
Signed-off-by: Alban Bedel
Acked-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1453553867-27003-2-git-send-email-albeu@free.fr
Signed-off-by: Jason Cooper -
The driver stays the same but the initialization changes a bit.
For OF boards we now get the memory map from the OF node and use
a linear mapping instead of the legacy mapping. For legacy boards
we still use a legacy mapping and just pass down all the parameters
from the board init code.Signed-off-by: Alban Bedel
Acked-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.fr
Signed-off-by: Jason Cooper -
Instead of building the irq-armada-370-xp driver directly when
CONFIG_ARCH_MVEBU is enabled, this commit introduces an intermediate
CONFIG_ARMADA_370_XP_IRQ hidden Kconfig option.This allows this option to select other interrupt-related Kconfig
options (which will be needed in follow-up commits) rather than having
such selects done from arch/arm/mach-/.Signed-off-by: Thomas Petazzoni
Acked-by: Gregory CLEMENT
Link: https://lkml.kernel.org/r/1455115621-22846-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper
08 Feb, 2016
1 commit
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Add the BCM6345 interrupt controller based on the SMP-capable BCM7038
and the BCM3380 but with packed interrupt registers.Add the BCM6345 interrupt controller to a list with the existing BCM7038
so that interrupts on CPU1 are not ignored.Update the maintainers file list for BMIPS to include this driver.
Signed-off-by: Simon Arlott
Cc: Mark Rutland
Cc: devicetree@vger.kernel.org
Cc: Ian Campbell
Cc: Florian Fainelli
Cc: Jason Cooper
Cc: Pawel Moll
Cc: linux-mips@linux-mips.org
Cc: Marc Zyngier
Cc: Kevin Cernekee
Cc: Ralf Baechle
Cc: Jonas Gorski
Cc: Kumar Gala
Cc: Rob Herring
Link: http://lkml.kernel.org/r/5651D176.6030908@simon.arlott.org.uk
Signed-off-by: Thomas Gleixner
25 Jan, 2016
1 commit
-
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for 4.5 plus some 4.4 fixes.The executive summary:
- ATH79 platform improvments, use DT bindings for the ATH79 USB PHY.
- Avoid useless rebuilds for zboot.
- jz4780: Add NEMC, BCH and NAND device tree nodes
- Initial support for the MicroChip's DT platform. As all the device
drivers are missing this is still of limited use.
- Some Loongson3 cleanups.
- The unavoidable whitespace polishing.
- Reduce clock skew when synchronizing the CPU cycle counters on CPU
startup.
- Add MIPS R6 fixes.
- Lots of cleanups across arch/mips as fallout from KVM.
- Lots of minor fixes and changes for IEEE 754-2008 support to the
FPU emulator / fp-assist software.
- Minor Ralink, BCM47xx and bcm963xx platform support improvments.
- Support SMP on BCM63168"* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits)
MIPS: zboot: Add support for serial debug using the PROM
MIPS: zboot: Avoid useless rebuilds
MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB
MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function
MIPS: bcm963xx: Update bcm_tag field image_sequence
MIPS: bcm963xx: Move extended flash address to bcm_tag header file
MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure
MIPS: bcm63xx: nvram: Use nvram structure definition from header file
MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure
MAINTAINERS: Add KVM for MIPS entry
MIPS: KVM: Add missing newline to kvm_err()
MIPS: Move KVM specific opcodes into asm/inst.h
MIPS: KVM: Use cacheops.h definitions
MIPS: Break down cacheops.h definitions
MIPS: Use EXCCODE_ constants with set_except_vector()
MIPS: Update trap codes
MIPS: Move Cause.ExcCode trap codes to mipsregs.h
MIPS: KVM: Make kvm_mips_{init,exit}() static
MIPS: KVM: Refactor added offsetof()s
MIPS: KVM: Convert EXPORT_SYMBOL to _GPL
...
24 Jan, 2016
1 commit
-
This adds support for the interrupt controller present on PIC32 class
devices. It handles all internal and external interrupts. This controller
exists outside of the CPU core and is the arbitrator of all interrupts
(including interrupts from the CPU itself) before they are presented to
the CPU.The following features are supported:
- DT properties for EVIC and for devices/peripherals that use interrupt lines
- Persistent and non-persistent interrupt handling
- irqdomain and generic chip support
- Configuration of external interrupt edge polaritySigned-off-by: Cristian Birsan
Signed-off-by: Joshua Henderson
Acked-by: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12092/
Signed-off-by: Ralf Baechle
29 Dec, 2015
1 commit
-
This commit adds support for the TS-4800 interrupt controller. This
controller is instantiated in a companion FPGA, and multiplex interrupts
for other FPGA IPs.As this component is external to the SoC, the SoC might need to reserve
pins, so this controller is implemented as a platform driver and doesn't
use the IRQCHIP_DECLARE construct.Signed-off-by: Damien Riegel
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: kernel@savoirfairelinux.com
Link: http://lkml.kernel.org/r/1450728683-31416-2-git-send-email-damien.riegel@savoirfairelinux.com
Signed-off-by: Thomas Gleixner
19 Dec, 2015
1 commit
-
…arm-platforms into irq/core
Pull the GIC related updates from Marc Zyngier:
"Not a lot this time (what a relief!), but an interesting series from
Linus Walleij coming out of his work converting the ARM RealView
platforms to DT, and a couple of mundane fixes."
18 Dec, 2015
1 commit
-
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3Reviewed-by: Marc Zyngier
Signed-off-by: Ma Jun
Signed-off-by: Marc Zyngier
16 Dec, 2015
1 commit
-
The ARM RealView PB11MPCore reference design has some special
bits in a system controller register to set up the GIC in one
of three modes: legacy, new with DCC, new without DCC. The
register is also used to enable FIQ.Since the platform will not boot unless this register is set
up to "new with DCC" mode, we need a special quirk to be
compiled-in for the RealView platforms.If we find the right compatible string on the GIC TestChip,
we enable this quirk by looking up the system controller and
enabling the special bits.We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old
boardfile code has the same fix hardcoded, and this is only
needed for the attempts to modernize the RealView code using
device tree.After fixing this, the PB11MPCore boots with device tree
only.Cc: Thomas Gleixner
Cc: Jason Cooper
Signed-off-by: Linus Walleij
Signed-off-by: Marc Zyngier
14 Oct, 2015
1 commit
-
Freescale iMX23/iMX28 and Alphascale ASM9260 have similar interrupt
collectors. We already prepared the mxs driver to handle a different
register layout. Add the actual ASM9260 support.Differences between these devices:
- Different register offsets
- Different count of interupt lines per register
- ASM9260 does not provide reset bit
- ASM9260 does not support FIQ.Signed-off-by: Oleksij Rempel
Tested-by: Shawn Guo
Cc: Sascha Hauer
Cc: marc.zyngier@arm.com
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1444677334-12242-6-git-send-email-linux@rempel-privat.de
Signed-off-by: Thomas Gleixner
25 Aug, 2015
1 commit
-
IMX7D contains a new version of GPC IP block (GPCv2). It has two major
functions: power management and wakeup source management.When the system is in WFI (wait for interrupt) mode, the GPC block
will be the first block on the platform to be activated and signaled.In normal wait mode during cpu idle, the system can be woken up by any
enabled interrupts. In standby or suspend mode, the system can only be
wokem up by the pre-defined wakeup sources.Based-on-patch-by: Anson Huang
Signed-off-by: Shenwei Wang
Cc:
Cc:
Cc:
Link: http://lkml.kernel.org/r/1440443055-7291-1-git-send-email-shenwei.wang@freescale.com
Signed-off-by: Thomas Gleixner
21 Aug, 2015
1 commit
-
This interrupt controller is the new root interrupt controller with
the timer, PMU events, and IPIs, and the bcm2835's interrupt
controller is chained off of it to handle the peripherals.I wrote the interrupt chip support, while Andrea Merello wrote the IPI
code.Signed-off-by: Andrea Merello
Signed-off-by: Eric Anholt
Acked-by: Stephen Warren
Cc: linux-rpi-kernel@lists.infradead.org
Cc: Lee Jones
Cc: Jason Cooper
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1438902033-31477-5-git-send-email-eric@anholt.net
Signed-off-by: Thomas Gleixner
01 Aug, 2015
1 commit
-
Signed-off-by: Ralf Baechle
Signed-off-by: Thomas Gleixner
30 Jul, 2015
2 commits
-
In order to support non-PCI MSI with the GICv3 ITS, add the minimal
required entry points for the MSI domain (an msi_prepare implementation).The rest is only boilerplate code to find the raw ITS domain.
Signed-off-by: Marc Zyngier
Cc:
Cc: Yijing Wang
Cc: Ma Jun
Cc: Lorenzo Pieralisi
Cc: Duc Dang
Cc: Hanjun Guo
Cc: Bjorn Helgaas
Cc: Jiang Liu
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1438091186-10244-16-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
It is becoming obvious that having the PCI/MSI code in the same
file as the the core ITS code is giving people implementing non-PCI
MSI support the wrong kind of idea.In order to make things a bit clearer, let's move the PCI/MSI code
out to its own file. Hopefully it will make it clear that whoever
thinks of hooking into the core ITS better have a very strong point.We use a temporary entry point that will get removed in a subsequent
patch, once the proper infrastructure is added.Signed-off-by: Marc Zyngier
Cc:
Cc: Yijing Wang
Cc: Ma Jun
Cc: Lorenzo Pieralisi
Cc: Duc Dang
Cc: Hanjun Guo
Cc: Bjorn Helgaas
Cc: Jiang Liu
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1438091186-10244-12-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
28 Jun, 2015
1 commit
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Pull MIPS updates from Ralf Baechle:
- Improvements to the tlb_dump code
- KVM fixes
- Add support for appended DTB
- Minor improvements to the R12000 support
- Minor improvements to the R12000 support
- Various platform improvments for BCM47xx
- The usual pile of minor cleanups
- A number of BPF fixes and improvments
- Some improvments to the support for R3000 and DECstations
- Some improvments to the ATH79 platform support
- A major patchset for the JZ4740 SOC adding support for the CI20 platform
- Add support for the Pistachio SOC
- Minor BMIPS/BCM63xx platform support improvments.
- Avoid "SYNC 0" as memory barrier when unlocking spinlocks
- Add support for the XWR-1750 board.
- Paul's __cpuinit/__cpuinitdata cleanups.
- New Malta CPU board support large memory so enable ZONE_DMA32.* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits)
MIPS: spinlock: Adjust arch_spin_lock back-off time
MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA
MIPS: BCM47xx: Simplify handling SPROM revisions
MIPS: Cobalt Don't use module_init in non-modular MTD registration.
MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/
MIPS: use for_each_sg()
MIPS: BCM47xx: Don't select BCMA_HOST_PCI
MIPS: BCM47xx: Add helper variable for storing NVRAM length
MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
MIPS: Replace smp_mb with release barrier function in unlocks.
MIPS: i8259: DT support
MIPS: Malta: Basic DT plumbing
MIPS: include errno.h for ENODEV in mips-cm.h
MIPS: Define GCR_GIC_STATUS register fields
MIPS: BPF: Introduce BPF ASM helpers
MIPS: BPF: Use BPF register names to describe the ABI
MIPS: BPF: Move register definition to the BPF header
MIPS: net: BPF: Replace RSIZE with SZREG
MIPS: BPF: Free up some callee-saved registers
MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers
...