12 Jan, 2017

1 commit

  • commit 34c535793bcbf9263cf22f8a52101f796cdfab8e upstream.

    We did not implement an irq_cpu_offline callback for our irqchip, yet we
    support setting a given IRQ's affinity. This resulted in interrupts
    whose affinity mask included CPUs being taken offline not to work
    correctly once the CPU had been put offline.

    Fixes: 5f7f0317ed28 ("IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers")
    Signed-off-by: Florian Fainelli
    Cc: linux-mips@linux-mips.org
    Cc: jason@lakedaemon.net
    Cc: marc.zyngier@arm.com
    Cc: cernekee@gmail.com
    Cc: jaedon.shin@gmail.com
    Cc: ralf@linux-mips.org
    Cc: justinpopo6@gmail.com
    Link: http://lkml.kernel.org/r/1477948656-12966-2-git-send-email-f.fainelli@gmail.com
    Signed-off-by: Thomas Gleixner
    Signed-off-by: Greg Kroah-Hartman

    Florian Fainelli
     

12 Oct, 2016

1 commit

  • Kernel source files need not include explicitly
    because the top Makefile forces to include it with:

    -include $(srctree)/include/linux/kconfig.h

    This commit removes explicit includes except the following:

    * arch/s390/include/asm/facilities_src.h
    * tools/testing/radix-tree/linux/kernel.h

    These two are used for host programs.

    Link: http://lkml.kernel.org/r/1473656164-11929-1-git-send-email-yamada.masahiro@socionext.com
    Signed-off-by: Masahiro Yamada
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Masahiro Yamada
     

16 Sep, 2015

1 commit

  • Most interrupt flow handlers do not use the irq argument. Those few
    which use it can retrieve the irq number from the irq descriptor.

    Remove the argument.

    Search and replace was done with coccinelle and some extra helper
    scripts around it. Thanks to Julia for her help!

    Signed-off-by: Thomas Gleixner
    Cc: Julia Lawall
    Cc: Jiang Liu

    Thomas Gleixner
     

12 Jul, 2015

2 commits

  • Chained irq handlers usually set up handler data as well. We now have
    a function to set both under irq_desc->lock. Replace the two calls
    with one.

    Search and conversion was done with coccinelle:

    @@
    expression E1, E2, E3;
    @@
    (
    -if (irq_set_handler_data(E1, E2) != 0)
    - BUG();
    |
    -irq_set_handler_data(E1, E2);
    )
    -irq_set_chained_handler(E1, E3);
    +irq_set_chained_handler_and_data(E1, E3, E2);

    @@
    expression E1, E2, E3;
    @@
    (
    -if (irq_set_handler_data(E1, E2) != 0)
    - BUG();
    ...
    |
    -irq_set_handler_data(E1, E2);
    ...
    )
    -irq_set_chained_handler(E1, E3);
    +irq_set_chained_handler_and_data(E1, E3, E2);

    Reported-by: Russell King
    Signed-off-by: Thomas Gleixner
    Cc: Julia Lawall
    Cc: Kevin Cernekee
    Cc: Florian Fainelli
    Cc: Thomas Gleixner
    Cc: Jason Cooper
    Cc: linux-mips@linux-mips.org

    Thomas Gleixner
     
  • The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so
    the local irqchip.h became an empty shell, which solely includes
    include/linux/irqchip.h

    Include the global header in all irqchip drivers instead of the local
    header, so we can remove it.

    Signed-off-by: Joel Porquet
    Cc: vgupta@synopsys.com
    Cc: monstr@monstr.eu
    Cc: ralf@linux-mips.org
    Cc: jason@lakedaemon.net
    Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbook
    Signed-off-by: Thomas Gleixner

    Joel Porquet
     

01 Apr, 2015

1 commit

  • This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
    it has the following characteristics:

    - 64 to 160+ level IRQs
    - Atomic set/clear registers
    - Reasonably predictable register layout (N status words, then N
    mask status words, then N mask set words, then N mask clear words)
    - SMP affinity supported on most systems
    - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3

    This driver registers one IRQ domain and one IRQ chip to cover all
    instances of the block. Up to 4 instances of the block may appear, as
    it supports 4-way IRQ affinity on BCM7435.

    The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
    is used instead. So this driver is primarily intended for MIPS STB chips.

    Signed-off-by: Kevin Cernekee
    Cc: f.fainelli@gmail.com
    Cc: jaedon.shin@gmail.com
    Cc: abrestic@chromium.org
    Cc: tglx@linutronix.de
    Cc: jason@lakedaemon.net
    Cc: jogo@openwrt.org
    Cc: arnd@arndb.de
    Cc: computersforpeace@gmail.com
    Cc: linux-mips@linux-mips.org
    Cc: devicetree@vger.kernel.org
    Cc: linux-kernel@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/8844/
    Signed-off-by: Ralf Baechle

    Kevin Cernekee