17 Oct, 2016
1 commit
-
The GICv3 architecture specification mentions that a 64bit
register can be accessed using two 32bit accesses. What it
doesn't mention is that this is only guaranteed on a system
that implements AArch32, and a pure AArch64 system is allowed
not to support this. This causes issues with the GICR_TYPER
and GITS_TYPER registers, which are both RO 64bit registers.In order to solve this, this patch switches the TYPER accesses
to the gic_read_typer macro already used in other parts of the
driver. This makes sure that we always use a 64bit access on
64bit systems, and two 32bit accesses on 32bit system.Signed-off-by: Marc Zyngier
12 Oct, 2016
1 commit
-
Pull IOMMU updates from Joerg Roedel:
- support for interrupt virtualization in the AMD IOMMU driver. These
patches were shared with the KVM tree and are already merged through
that tree.- generic DT-binding support for the ARM-SMMU driver. With this the
driver now makes use of the generic DMA-API code. This also required
some changes outside of the IOMMU code, but these are acked by the
respective maintainers.- more cleanups and fixes all over the place.
* tag 'iommu-updates-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (40 commits)
iommu/amd: No need to wait iommu completion if no dte irq entry change
iommu/amd: Free domain id when free a domain of struct dma_ops_domain
iommu/amd: Use standard bitmap operation to set bitmap
iommu/amd: Clean up the cmpxchg64 invocation
iommu/io-pgtable-arm: Check for v7s-incapable systems
iommu/dma: Avoid PCI host bridge windows
iommu/dma: Add support for mapping MSIs
iommu/arm-smmu: Set domain geometry
iommu/arm-smmu: Wire up generic configuration support
Docs: dt: document ARM SMMU generic binding usage
iommu/arm-smmu: Convert to iommu_fwspec
iommu/arm-smmu: Intelligent SMR allocation
iommu/arm-smmu: Add a stream map entry iterator
iommu/arm-smmu: Streamline SMMU data lookups
iommu/arm-smmu: Refactor mmu-masters handling
iommu/arm-smmu: Keep track of S2CR state
iommu/arm-smmu: Consolidate stream map entry state
iommu/arm-smmu: Handle stream IDs more dynamically
iommu/arm-smmu: Set PRIVCFG in stage 1 STEs
iommu/arm-smmu: Support non-PCI devices with SMMUv3
...
16 Sep, 2016
1 commit
-
When an MSI doorbell is located downstream of an IOMMU, attaching
devices to a DMA ops domain and switching on translation leads to a rude
shock when their attempt to write to the physical address returned by
the irqchip driver faults (or worse, writes into some already-mapped
buffer) and no interrupt is forthcoming.Address this by adding a hook for relevant irqchip drivers to call from
their compose_msi_msg() callback, to swizzle the physical address with
an appropriatly-mapped IOVA for any device attached to one of our DMA
ops domains.Acked-by: Thomas Gleixner
Acked-by: Marc Zyngier
Signed-off-by: Robin Murphy
Signed-off-by: Will Deacon
13 Sep, 2016
3 commits
-
ITS is prepared for being initialized different than DT,
therefore we can initialize it in ACPI way. We collect register base
address from MADT table and pass mandatory info to firmware-agnostic
ITS init call.Use here IORT lib to register ITS domain which then can be found and
used on to build another PCI MSI domain in hierarchical stack domain.NOTE: Waiting for proper ITS and NUMA node relation description in IORT
table, we pass around NUMA_NO_NODE to the its_probe_one init call.
This means that Cavium ThunderX erratum 23144 (pass1.1 only)
is not supported for ACPI boot method yet.Signed-off-by: Tomasz Nowicki
Acked-by: Marc Zyngier
Reviewed-by: Hanjun Guo
Signed-off-by: Marc Zyngier -
In order to add ACPI support we need to isolate ACPI&DT common code and
move DT logic to corresponding functions. To achieve this we are using
firmware agnostic handle which can be unpacked to either DT or ACPI node.No functional changes other than a very minor one:
1. Terminate its_init call with -ENODEV for non-DT case which allows
to remove hack from its-gic-v3.c.
2. Fix ITS base register address type (from 'unsigned long' to 'phys_addr_t'),
as a bonus we get nice string formatting.
3. Since there is only one of ITS parent domain convert it to static global
variable and drop the parameter from its_probe_one. Users can refer to it
in more convenient way then.Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
Signed-off-by: Marc Zyngier -
There is no point to initialize ITS without having msi-controller
property in corresponding DT node. However, its_probe is checking
msi-controller presence at the end, so we can save our time and do that
check prior to its_probe call. Also, for the code clarity purpose,
we put domain initialization to separate function.Signed-off-by: Tomasz Nowicki
Acked-by: Marc Zyngier
Reviewed-by: Hanjun Guo
Signed-off-by: Marc Zyngier
19 Aug, 2016
1 commit
-
When starting a kexec/kdump kernel, the GIC ITS will already have been
enabled. According to the ARM Generic Interrupt Controller
Architecture Specification (GIC architecture Version 3.0 and version
4.0), writing to GITS_BASER or GITS_CBASER is "UNPREDICTABLE" when
the ITS is enabled. On Cavium Thunder systems, this prevents the ITS
from being initializing in the kexec/kdump kernel, resulting in
failure to register/enable interrupts for all devices.The fix is to disable the ITS if it is not already in the disabled
state. This allows the ITS to be properly initialized and then
re-enabled in the kexec/kdump kernel.Acked-by: Marc Zyngier
Signed-off-by: David Daney
Signed-off-by: Marc Zyngier
13 Jun, 2016
5 commits
-
Since device IDs are extremely sparse, the single, a.k.a flat table is
not sufficient for the following two reasons.1) According to ARM-GIC spec, ITS hw can access maximum of 256(pages)*
64K(pageszie) bytes. In the best case, it supports upto DEVid=21
sparse with minimum device table entry size 8bytes.2) The maximum memory size that is possible without memblock depends on
MAX_ORDER. 4MB on 4K page size kernel with default MAX_ORDER, so it
supports DEVid range 19bits.The two-level device table feature brings us two advantages, the first
is a very high possibility of supporting upto 32bit sparse, and the
second one is the best utilization of memory allocation.The feature is enabled automatically during driver probe if the memory
requirement is more than 2*ITS-pages and the hardware is capable of
two-level table walk.Signed-off-by: Shanker Donthineni
Signed-off-by: Marc Zyngier -
No references to argument 'node_name' after modifying pr_xxx()
messages to include ITS base address instead of 'node_name'.Signed-off-by: Shanker Donthineni
Signed-off-by: Marc Zyngier -
The function is getting out of control, it has too many goto
statements and would be too complicated for adding a feature
two-level device table. So, it is time for us to cleanup and
move some of the logic to a separate function without affecting
the existing functionality.Signed-off-by: Shanker Donthineni
Signed-off-by: Marc Zyngier -
Only the device table BASERn needs to be handled differently as
compared to all other tables. So, adding a separate function for
easy code maintenance and improved code readability.Signed-off-by: Shanker Donthineni
Signed-off-by: Marc Zyngier -
This patch adds the two handy helper functions for reading and writing
ITS BASERn register.Signed-off-by: Shanker Donthineni
[Marc: Folded its_write_baser_cache into its_write_baser]
Signed-off-by: Marc Zyngier
03 Jun, 2016
1 commit
-
The erratum fixes the hang of ITS SYNC command by avoiding inter node
io and collections/cpu mapping on thunderx dual-socket platform.This fix is only applicable for Cavium's ThunderX dual-socket platform.
Reviewed-by: Robert Richter
Signed-off-by: Ganapatrao Kulkarni
Signed-off-by: Robert Richter
Signed-off-by: Marc Zyngier
11 May, 2016
1 commit
-
We are not checking whether the requested device identifier fits into
the device table memory or not. The function its_create_device()
assumes that enough memory has been allocated for whole DevID space
(reported by ITS_TYPER.Devbits) during the ITS probe() and continues
to initialize ITS hardware.This assumption is not perfect, sometimes we reduce memory size either
because of its size crossing MAX_ORDER-1 or BASERn max size limit. The
MAPD command fails if 'Device ID' is outside of device table range.Add a simple validation check to avoid MAPD failures since we are
not handling ITS command errors. This change also helps to return an
error -ENOMEM instead of success to caller.Signed-off-by: Shanker Donthineni
Signed-off-by: Marc Zyngier
09 Mar, 2016
2 commits
-
gicv3_init_bases() is the only caller for its_init(),
also it is a __init function, so mark its_init() as __init too,
then recursively mark the functions called as __init.This will help to introduce ITS initialization using ACPI tables as
we will use acpi_table_parse_entries family functions there which
belong to __init section as well.Acked-by: Marc Zyngier
Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
Signed-off-by: Marc Zyngier -
The gic_root_node variable defined in ITS driver is not actually
used, so just remove it.Acked-by: Marc Zyngier
Signed-off-by: Hanjun Guo
Signed-off-by: Marc Zyngier
18 Feb, 2016
1 commit
-
Function its_alloc_tables() maintains two local variables, "order" and
and "alloc_size", to hold memory size that has been allocated to
ITS_BASEn. We don't always refresh the variable alloc_size whenever
value of the variable order changes, causing the following two
problems.- Cache flush operation with size more than required.
- Information reported by pr_info is not correct.Use a helper macro that converts page order to size in bytes instead of
variable "alloc_size" to fix both the problems.Signed-off-by: Shanker Donthineni
Signed-off-by: Marc Zyngier
12 Feb, 2016
1 commit
-
When the GIC is using EOImode==1, the EOI is done immediately,
leaving the deactivation to be performed when the EOI was
previously done.Unfortunately, the ITS is not aware of the EOImode at all, and
blindly EOIs the interrupt again. On most systems, this is ignored
(despite being a programming error), but some others do raise a
SError exception as there is no priority drop to perform for this
interrupt.The fix is to stop trying to be clever, and always call into the
underlying GIC to perform the right access, irrespective of the
more we're in.[Marc: Reworked commit message]
Fixes: 0b996fd35957a ("irqchip/GICv3: Convert to EOImode == 1")
Cc: stable@vger.kernel.org
Acked-by: Marc Zyngier
Signed-off-by: Ashok Kumar
Signed-off-by: Marc Zyngier
04 Feb, 2016
1 commit
-
The current ITS driver has a memory leak in its_free_tables(). It
happens on tear down path of the driver when its_probe() call fails.
its_free_tables() should free the exact number of pages that have
been allocated, not just a single page as current code does.This patch records the memory size for each ITS_BASERn at the time of
page allocation and uses the same size information when freeing pages
to fix the issue.Signed-off-by: Shanker Donthineni
Acked-by: Marc Zyngier
Cc: Jason Cooper
Cc: Vikram Sethi
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1454379584-21772-1-git-send-email-shankerd@codeaurora.org
Signed-off-by: Thomas Gleixner
26 Jan, 2016
1 commit
-
When the programming of a GITS_BASERn register fails because of
an unsupported ITS page size, we retry it with a smaller page size.
Unfortunately, we don't recompute the number of allocated ITS pages,
indicating the wrong value computed in the original allocation.A convenient fix is to free the pages we allocated, update the
page size, and restart the allocation. This will ensure that
we always allocate the right amount in the case of a device
table, specially if we have to reduce the allocation order
to stay within the boundaries of the ITS maximum allocation.Reported-and-tested-by: Ma Jun
Signed-off-by: Marc Zyngier
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1453818255-1289-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
14 Oct, 2015
3 commits
-
Since we now have a generic data structure to express an
interrupt specifier, convert all hierarchical irqchips that
are OF based to use a fwnode_handle as part of their alloc
and xlate (which becomes translate) callbacks.As most of these drivers have dependencies (they exchange IRQ
specifiers), change them all in a single, massive patch...Signed-off-by: Marc Zyngier
Reviewed-and-tested-by: Hanjun Guo
Tested-by: Lorenzo Pieralisi
Cc:
Cc: Tomasz Nowicki
Cc: Suravee Suthikulpanit
Cc: Graeme Gregory
Cc: Jake Oshins
Cc: Jiang Liu
Cc: Jason Cooper
Cc: Rafael J. Wysocki
Link: http://lkml.kernel.org/r/1444737105-31573-6-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
The struct irq_domain contains a "struct device_node *" field
(of_node) that is almost the only link between the irqdomain
and the device tree infrastructure.In order to prepare for the removal of that field, convert all
users to use irq_domain_get_of_node() instead.Signed-off-by: Marc Zyngier
Reviewed-and-tested-by: Hanjun Guo
Tested-by: Lorenzo Pieralisi
Cc:
Cc: Tomasz Nowicki
Cc: Suravee Suthikulpanit
Cc: Graeme Gregory
Cc: Jake Oshins
Cc: Jiang Liu
Cc: Jason Cooper
Cc: Rafael J. Wysocki
Link: http://lkml.kernel.org/r/1444737105-31573-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
Bring in upstream updates for patches which depend on them
03 Oct, 2015
1 commit
-
More agressive inlining in recent versions of GCC have uncovered
a new set of warnings:drivers/irqchip/irq-gic-v3-its.c: In function its_msi_prepare:
drivers/irqchip/irq-gic-v3-its.c:1148:26: warning: lpi_base may be used
uninitialized in this function [-Wmaybe-uninitialized]
dev->event_map.lpi_base = lpi_base;
^
drivers/irqchip/irq-gic-v3-its.c:1116:6: note: lpi_base was declared here
int lpi_base;
^
drivers/irqchip/irq-gic-v3-its.c:1149:25: warning: nr_lpis may be used
uninitialized in this function [-Wmaybe-uninitialized]
dev->event_map.nr_lpis = nr_lpis;
^
drivers/irqchip/irq-gic-v3-its.c:1117:6: note: nr_lpis was declared here
int nr_lpis;
^
The warning is fairly benign (there is no code path that could
actually use uninitialized variables), but let's silence it anyway
by zeroing the variables on the error path.Reported-by: Alex Shi
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Cc: linux-arm-kernel@lists.infradead.org
Cc: David Daney
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1443800646-8074-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
29 Sep, 2015
4 commits
-
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access typeThe fixes are in ITS initialization and basically ignore memory access
type and table size provided by the TYPER and BASER registers.Signed-off-by: Ganapatrao Kulkarni
Signed-off-by: Robert Richter
Reviewed-by: Marc Zygnier
Acked-by: Catalin Marinas
Cc: Tirumalesh Chalamarla
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper
Cc: Will Deacon
Link: http://lkml.kernel.org/r/1442869119-1814-6-git-send-email-rric@kernel.org
Signed-off-by: Thomas Gleixner -
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. A function is added that reads the IIDR registers
for ITS (GITS_IIDR) and then goes through a list of init functions to
be called for specific versions. Same could be done for GICV3
(GICD_IIDR), but there are no users yet for it.The patch is needed to implement workarounds for HW errata in Cavium's
ThunderX GICV3 ITS.Signed-off-by: Robert Richter
Reviewed-by: Marc Zygnier
Acked-by: Catalin Marinas
Cc: Tirumalesh Chalamarla
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1442869119-1814-5-git-send-email-rric@kernel.org
Signed-off-by: Thomas Gleixner -
No need to read the typer register in the loop. Values do not change.
This patch is basically a prerequisite for a follow-on patch that adds
errata code for Cavium ThunderX. It moves the calculation of the
number of id entries to the beginning of the function close to other
setup values that are needed to allocate the its table. Now we have a
central location to modify the setup parameters and the errata code
can be implemented in a single block.Signed-off-by: Robert Richter
Acked-by: Marc Zyngier
Acked-by: Catalin Marinas
Cc: Tirumalesh Chalamarla
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1442869119-1814-4-git-send-email-rric@kernel.org
Signed-off-by: Thomas Gleixner -
The number of pages for the its table may exceed the maximum of 256.
Adding a range check and limitting the number to its maximum.Based on a patch from Tirumalesh Chalamarla .
Signed-off-by: Tirumalesh Chalamarla
Signed-off-by: Robert Richter
Reviewed-by: Marc Zyngier
Acked-by: Catalin Marinas
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1442869119-1814-2-git-send-email-rric@kernel.org
Signed-off-by: Thomas Gleixner
15 Sep, 2015
1 commit
-
When the ITS is configured for non-cacheable transactions, make sure
that the allocated, zeroed memory is flushed to the Point of
Coherency, allowing the ITS to observe the zeros instead of random
garbage (or even get its own data overwritten by zeros being evicted
from the cache...).Fixes: 241a386c7dbb "irqchip: gicv3-its: Use non-cacheable accesses when no shareability"
Reported-and-tested-by: Stuart Yoder
Signed-off-by: Marc Zyngier
Cc: linux-arm-kernel@lists.infradead.org
Cc: Pavel Fedin
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1442142873-20213-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
30 Jul, 2015
5 commits
-
We can now lookup the base ITS domain, making it possible to
initialize the PCI/MSI code independently from the main ITS
subsystem.This allows us to remove all the previously add hooks.
Signed-off-by: Marc Zyngier
Cc:
Cc: Yijing Wang
Cc: Ma Jun
Cc: Lorenzo Pieralisi
Cc: Duc Dang
Cc: Hanjun Guo
Cc: Bjorn Helgaas
Cc: Jiang Liu
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1438091186-10244-15-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
The GICv3 ITS only uses the msi_controller structure as a way
to match the host bridge with its MSI HW, and thus the msi_domain.
But now that we can directly associate an msi_domain with a device,
there is no use keeping this msi_controller around.Just remove all traces of msi_controller from the driver.
Signed-off-by: Marc Zyngier
Cc:
Cc: Yijing Wang
Cc: Ma Jun
Cc: Lorenzo Pieralisi
Cc: Duc Dang
Cc: Hanjun Guo
Cc: Bjorn Helgaas
Cc: Jiang Liu
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1438091186-10244-14-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
Now that we can distinguish between multiple domains carrying the
same device_node, tag the raw ITS domain with DOMAIN_BUS_NEXUS.
This will allow MSI providers built on top of the raw ITS domain
to identify it.Signed-off-by: Marc Zyngier
Cc:
Cc: Yijing Wang
Cc: Ma Jun
Cc: Lorenzo Pieralisi
Cc: Duc Dang
Cc: Hanjun Guo
Cc: Bjorn Helgaas
Cc: Jiang Liu
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1438091186-10244-13-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
It is becoming obvious that having the PCI/MSI code in the same
file as the the core ITS code is giving people implementing non-PCI
MSI support the wrong kind of idea.In order to make things a bit clearer, let's move the PCI/MSI code
out to its own file. Hopefully it will make it clear that whoever
thinks of hooking into the core ITS better have a very strong point.We use a temporary entry point that will get removed in a subsequent
patch, once the proper infrastructure is added.Signed-off-by: Marc Zyngier
Cc:
Cc: Yijing Wang
Cc: Ma Jun
Cc: Lorenzo Pieralisi
Cc: Duc Dang
Cc: Hanjun Guo
Cc: Bjorn Helgaas
Cc: Jiang Liu
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1438091186-10244-12-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
Pull in upstream fixes before applying conflicting changes
17 Jul, 2015
1 commit
-
The GICv3 ITS architecture allows a given [DevID, EventID] pair to be
translated to a [LPI, Collection] pair, where DevID is the device writing
the MSI, EventID is the payload being written, LPI is the actual
interrupt number, and Collection is roughly equivalent to a target CPU.Each LPI can be mapped to a separate collection, but the ITS driver
insists on maintaining the collection on a device basis, instead of doing
it on a per interrupt basis.This is obviously flawed, and this patch fixes it by adding a per interrupt
index that indicates which collection number is in use.Reported-by: Ian Campbell
Signed-off-by: Marc Zyngier
Cc:
Cc: Jason Cooper
Cc: stable@vger.kernel.org # 4.1, 4.0
Link: http://lkml.kernel.org/r/1437126402-11677-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
12 Jul, 2015
1 commit
-
The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so
the local irqchip.h became an empty shell, which solely includes
include/linux/irqchip.hInclude the global header in all irqchip drivers instead of the local
header, so we can remove it.Signed-off-by: Joel Porquet
Cc: vgupta@synopsys.com
Cc: monstr@monstr.eu
Cc: ralf@linux-mips.org
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbook
Signed-off-by: Thomas Gleixner
21 May, 2015
1 commit
-
When allocating a device table, if the requested allocation is smaller
than the default granule size of the ITS then, we need to round up to
the default size.Signed-off-by: Minghuan Lian
[ stuart: Added comments and massaged changelog ]
Signed-off-by: Stuart Yoder
Reviewed-by: Marc Zygnier
Cc:
Cc:
Link: http://lkml.kernel.org/r/1432134795-661-1-git-send-email-stuart.yoder@freescale.com
Signed-off-by: Thomas Gleixner
30 Mar, 2015
3 commits
-
If the ITS or the redistributors report their shareability as zero,
then it is important to make sure they will no generate any cacheable
traffic, as this is unlikely to produce the expected result.Signed-off-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1427465705-17126-5-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper -
The ITS driver sometime mixes up the use of GICR_PROPBASE bitfields
for the GICR_PENDBASE register, and GITS_BASER for GICR_CBASE.This does not lead to any observable bug because similar bits are
at the same location, but this just make the code even harder to
understand...This patch provides the required #defines and fixes the mixup.
Signed-off-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1427465705-17126-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper -
When building ITS commands which have the device ID in it, we
should mask off the whole upper 32 bits of the first command word
before inserting the new value in there.Signed-off-by: Andre Przywara
Signed-off-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1427465705-17126-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper
