16 Sep, 2015
1 commit
-
Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.Remove the argument.
Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!Signed-off-by: Thomas Gleixner
Cc: Julia Lawall
Cc: Jiang Liu
12 Jul, 2015
3 commits
-
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
already have a pointer to corresponding irq_desc.Signed-off-by: Jiang Liu
Cc: Konrad Rzeszutek Wilk
Cc: Tony Luck
Cc: linux-arm-kernel@lists.infradead.org
Cc: Bjorn Helgaas
Cc: Benjamin Herrenschmidt
Cc: Randy Dunlap
Cc: Yinghai Lu
Cc: Borislav Petkov
Cc: Jason Cooper
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Cc: Maxime Ripard
Link: http://lkml.kernel.org/r/1433391238-19471-11-git-send-email-jiang.liu@linux.intel.com
Signed-off-by: Thomas Gleixner -
Chained irq handlers usually set up handler data as well. We now have
a function to set both under irq_desc->lock. Replace the two calls
with one.Search and conversion was done with coccinelle:
@@
expression E1, E2, E3;
@@
(
-if (irq_set_handler_data(E1, E2) != 0)
- BUG();
|
-irq_set_handler_data(E1, E2);
)
-irq_set_chained_handler(E1, E3);
+irq_set_chained_handler_and_data(E1, E3, E2);@@
expression E1, E2, E3;
@@
(
-if (irq_set_handler_data(E1, E2) != 0)
- BUG();
...
|
-irq_set_handler_data(E1, E2);
...
)
-irq_set_chained_handler(E1, E3);
+irq_set_chained_handler_and_data(E1, E3, E2);Reported-by: Russell King
Signed-off-by: Thomas Gleixner
Cc: Julia Lawall
Cc: Thomas Gleixner
Cc: Jason Cooper -
The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so
the local irqchip.h became an empty shell, which solely includes
include/linux/irqchip.hInclude the global header in all irqchip drivers instead of the local
header, so we can remove it.Signed-off-by: Joel Porquet
Cc: vgupta@synopsys.com
Cc: monstr@monstr.eu
Cc: ralf@linux-mips.org
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbook
Signed-off-by: Thomas Gleixner
03 Sep, 2014
1 commit
-
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1409047421-27649-11-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper
08 May, 2014
1 commit
-
Non-DT irq handlers were working through irq causes from most-significant
to least-significant bit, while DT irqchip driver does it the other way
round. This revealed some more HW issues on Kirkwood peripheral IP, where
spurious sdio irqs can happen although irqs are masked.Also, the generated binaries show that original non-DT order compared
to DT order save two instructions for each bit count check:irqchip DT order with ffs():
60: e3a06001 mov r6, #1
64: e2643000 rsb r3, r4, #0
68: e0033004 and r3, r3, r4
6c: e16f3f13 clz r3, r3
70: e263301f rsb r3, r3, #31
74: e1c44316 bic r4, r4, r6, lsl r3
78: e5971004 ldr r1, [r7, #4]Original non-DT order with fls():
60: e3a07001 mov r7, #1
64: e16f3f14 clz r3, r4
68: e263301f rsb r3, r3, #31
6c: e1c44317 bic r4, r4, r7, lsl r3
70: e5951004 ldr r1, [r5, #4]Therefore, reverse irq bit handling back to original order by replacing
ffs() with fls().Signed-off-by: Sebastian Hesselbarth
Link: https://lkml.kernel.org/r/1398719528-23607-1-git-send-email-sebastian.hesselbarth@gmail.com
Acked-by: Jason Cooper
Signed-off-by: Jason Cooper
12 Mar, 2014
2 commits
-
Merge the request/release callbacks which are in a separate branch for
consumption by the gpio folks.Signed-off-by: Thomas Gleixner
-
LTO patches add __visible to the asmlinkage define, causing
compilation warnings like:drivers/irqchip/irq-gic.c:283:1: warning: 'externally_visible'
attribute have effect only on public objects [-Wattributes]Drop asmlinkage here to avoid such warnings.
Reported-by: Olof's autobuilder
Signed-off-by: Stephen Boyd
Cc: linux-arm-kernel@lists.infradead.org
Cc: khilman@linaro.org
Cc: Russell King
Cc: Josh Cartwright
Cc: Andi Kleen
Link: http://lkml.kernel.org/r/1393980030-17770-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner
22 Feb, 2014
1 commit
-
Enabling SPARSE_IRQ shows up a bug in the irq-orion bridge interrupt
handler. The bridge interrupt is implemented using a single generic
chip. Thus the parameter passed to irq_get_domain_generic_chip()
should always be zero.Signed-off-by: Andrew Lunn
Acked-by: Sebastian Hesselbarth
Fixes: 9dbd90f17e4f ("irqchip: Add support for Marvell Orion SoCs")
Cc: # v3.11+
Signed-off-by: Jason Cooper
07 Feb, 2014
3 commits
-
Bridge IRQ_CAUSE bits are asserted regardless of the corresponding bit in
IRQ_MASK register. To avoid interrupt events on stale irqs, we have to clear
them before unmask. This installs an .irq_startup callback to ensure stale
irqs are cleared before initial unmask.Signed-off-by: Sebastian Hesselbarth
Tested-by: Ezequiel Garcia
Cc: : f56c0738b5c2: "irqchip: orion: clear bridge cause register on init"
Cc: : 38bd80b84fca: "irqchip: orion: use handle_edge_irq on bridge irqs"
Cc: # v3.10+
Signed-off-by: Jason Cooper -
Bridge irqs are edge-triggered, i.e. they get asserted on low-to-high
transitions and not on the level of the downstream interrupt line.
This replaces handle_level_irq by the more appropriate handle_edge_irq.Signed-off-by: Sebastian Hesselbarth
Tested-by: Ezequiel Garcia
Cc: : f56c0738b5c2: "irqchip: orion: clear bridge cause register on init"
Cc: # v3.10+
Signed-off-by: Jason Cooper -
It is good practice to mask and clear pending irqs on init. We already
mask all irqs, so also clear the bridge irq cause register.Signed-off-by: Sebastian Hesselbarth
Tested-by: Ezequiel Garcia
Cc: # v3.10+
Signed-off-by: Jason Cooper
11 Jun, 2013
1 commit
-
This patch adds an irqchip driver for the main interrupt controller found
on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
Corresponding device tree documentation is also added.Signed-off-by: Sebastian Hesselbarth
Acked-by: Grant Likely
Cc: Rob Herring
Cc: Rob Landley
Cc: John Stultz
Cc: Russell King
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Thomas Petazzoni
Cc: Gregory Clement
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1370536034-23956-2-git-send-email-sebastian.hesselbarth@gmail.com
Signed-off-by: Thomas Gleixner