25 Nov, 2015
3 commits
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If the Renesas External IRQ Pin driver cannot find a functional clock,
it prints a warning, .e.g.renesas_intc_irqpin fe78001c.interrupt-controller: unable to get clock
and continues, as the clock is optional, depending on the SoC type.
This warning may confuse users.To fix this, add a flag to indicate that the clock is mandatory or
optional, and add a few more compatible entries:
- If the clock is mandatory (on R-Mobile A1 or SH-Mobile AG5), a
missing clock is now treated as a fatal error,
- If the clock is optional (on R-Car Gen1, or using the generic
"renesas,intc-irqpin" compatible value), the warning is no longer
printed.This requires making struct intc_irqpin_irlm_config more generic by
renaming it to intc_irqpin_config, and adding a flag to indicate if IRLM
is needed.
The new clock flag is merged with the existing shared_irqs boolean into
a bitfield to save space.Suggested-by: Magnus Damm
Signed-off-by: Geert Uytterhoeven
Link: https://lkml.kernel.org/r/1448377693-19597-1-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper -
intc_irqpin_priv.number_of_irqs is used inside intc_irqpin_probe() only,
so it can just become a local variable.Signed-off-by: Geert Uytterhoeven
Acked-by: Marc Zyngier
Acked-by: Thomas Gleixner
Link: https://lkml.kernel.org/r/1448376581-9202-3-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper -
Since commit 4baadb9e05c68962 ("ARM: shmobile: r8a7778: remove obsolete
setup code"), all Renesas SoCs with a renesas-intc-irqpin module are
only supported in generic DT-only ARM multi-platform builds. The driver
doesn't need to use platform data anymore, hence remove platform data
configuration.Signed-off-by: Geert Uytterhoeven
Acked-by: Marc Zyngier
Acked-by: Thomas Gleixner
Link: https://lkml.kernel.org/r/1448376581-9202-2-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper
01 Oct, 2015
1 commit
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Works the same as on r8a7779.
Signed-off-by: Ulrich Hecht
Signed-off-by: Geert Uytterhoeven
Cc: Jason Cooper
Cc: Marc Zyngier
Link: http://lkml.kernel.org/r/1443607387-19147-1-git-send-email-geert+Brenesas@glider.be
Signed-off-by: Thomas Gleixner
16 Sep, 2015
1 commit
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set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOENFor IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.Signed-off-by: Rob Herring
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King
Cc: Jason Cooper
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Cc: Stephen Warren
Cc: Lee Jones
Cc: Alexander Shiyan
Cc: Maxime Ripard
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Link: http://lkml.kernel.org/r/1440889285-5637-3-git-send-email-robh@kernel.org
Signed-off-by: Thomas Gleixner
15 Sep, 2015
2 commits
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The renesas-intc-irqpin interrupt controller is cascaded to the GIC, but
its driver doesn't propagate wake-up settings to the parent interrupt
controller.Since commit aec89ef72ba6c944 ("irqchip/gic: Enable SKIP_SET_WAKE and
MASK_ON_SUSPEND"), the GIC driver masks interrupts during suspend, and
wake-up through gpio-keys now fails on r8a7740/armadillo and
sh73a0/kzm9g.Fix this by propagating wake-up settings to the parent interrupt
controller. There's no need to handle irq_set_irq_wake() failures, as
the renesas-intc-irqpin interrupt controller is always cascaded to a
GIC, and the GIC driver always sets SKIP_SET_WAKE since the
aforementioned commit.Signed-off-by: Geert Uytterhoeven
Cc: Sudeep Holla
Cc: Magnus Damm
Cc: Jason Cooper
Cc: Marc Zyngier
Link: http://lkml.kernel.org/r/1441731636-17610-2-git-send-email-geert%2Brenesas@glider.be
Signed-off-by: Thomas Gleixner -
The renesas-intc-irqpin interrupt controller is cascaded to the GIC.
Hence when propagating wake-up settings to its parent interrupt
controller, the following lockdep warning is printed:=============================================
[ INFO: possible recursive locking detected ]
4.2.0-armadillo-10725-g50fcd7643c034198 #781 Not tainted
---------------------------------------------
s2ram/1179 is trying to acquire lock:
(&irq_desc_lock_class){-.-...}, at: [] __irq_get_desc_lock+0x78/0x94but task is already holding lock:
(&irq_desc_lock_class){-.-...}, at: [] __irq_get_desc_lock+0x78/0x94other info that might help us debug this:
Possible unsafe locking scenario:CPU0
----
lock(&irq_desc_lock_class);
lock(&irq_desc_lock_class);*** DEADLOCK ***
May be due to missing lock nesting notation
7 locks held by s2ram/1179:
#0: (sb_writers#7){.+.+.+}, at: [] __sb_start_write+0x64/0xb8
#1: (&of->mutex){+.+.+.}, at: [] kernfs_fop_write+0x78/0x1a0
#2: (s_active#23){.+.+.+}, at: [] kernfs_fop_write+0x80/0x1a0
#3: (autosleep_lock){+.+.+.}, at: [] pm_autosleep_lock+0x18/0x20
#4: (pm_mutex){+.+.+.}, at: [] pm_suspend+0x54/0x248
#5: (&dev->mutex){......}, at: [] __device_suspend+0xdc/0x240
#6: (&irq_desc_lock_class){-.-...}, at: [] __irq_get_desc_lock+0x78/0x94stack backtrace:
CPU: 0 PID: 1179 Comm: s2ram Not tainted 4.2.0-armadillo-10725-g50fcd7643c034198Hardware name: Generic R8A7740 (Flattened Device Tree)
[] (dump_backtrace) from [] (show_stack+0x18/0x1c)
[] (show_stack) from [] (dump_stack+0x20/0x28)
[] (dump_stack) from [] (__lock_acquire+0x67c/0x1b88)
[] (__lock_acquire) from [] (lock_acquire+0x9c/0xbc)
[] (lock_acquire) from [] (_raw_spin_lock_irqsave+0x44/0x58)
[] (_raw_spin_lock_irqsave) from [] (__irq_get_desc_lock+0x78/0x94
[] (__irq_get_desc_lock) from [] (irq_set_irq_wake+0x28/0x100)
[] (irq_set_irq_wake) from [] (intc_irqpin_irq_set_wake+0x24/0x4c)
[] (intc_irqpin_irq_set_wake) from [] (set_irq_wake_real+0x3c/0x50
[] (set_irq_wake_real) from [] (irq_set_irq_wake+0x64/0x100)
[] (irq_set_irq_wake) from [] (gpio_keys_suspend+0x60/0xa0)
[] (gpio_keys_suspend) from [] (platform_pm_suspend+0x3c/0x5c)Avoid this false positive by using a separate lockdep class for INTC
External IRQ Pin interrupts.Signed-off-by: Geert Uytterhoeven
Cc: Grygorii Strashko
Cc: Magnus Damm
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1441798974-25716-3-git-send-email-geert%2Brenesas@glider.be
Signed-off-by: Thomas Gleixner
05 May, 2015
1 commit
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The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.Signed-off-by: Krzysztof Kozlowski
Cc: Jason Cooper
Cc: Kukjin Kim
Cc: Stephen Warren
Cc: Lee Jones
Cc: Matthias Brugger
Cc: Maxime Ripard
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Link: http://lkml.kernel.org/r/1430139264-4362-2-git-send-email-k.kozlowski.k@gmail.com
Signed-off-by: Thomas Gleixner
26 Jan, 2015
1 commit
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Add r8a7779 specific support for IRLM bit configuration
in the INTC-IRQPIN driver. Without this code we need
special workaround code in arch/arm/mach-shmobile.The IRLM bit for the INTC hardware exists on various
older SH-based SoCs and is used to select between two
modes for the external interrupt pins IRQ0 to IRQ3:IRLM = 0: (default from reset on r8a7779)
In this mode the pins IRQ0 to IRQ3 are used together
to give a value between 0 and 15 to the SoC. External
logic is required for masking. This mode is not
supported by the INTC-IRQPIN driver.IRLM = 1: (needs this patch or configuration elsewhere)
In this mode IRQ0 to IRQ3 operate as 4 individual
external interrupt pins. In this mode the SMSC ethernet
chip can be used via IRQ1 on r8a7779 Marzen. This mode
is the only supported mode by the INTC-IRQPIN driver.For this patch to work the r8a7779 DTS needs to pass
the ICR0 register as the last register bank.Signed-off-by: Magnus Damm
Cc: Magnus Damm
Cc: horms@verge.net.au
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/20141203121803.5936.35881.sendpatchset@w520
Signed-off-by: Thomas Gleixner
20 Oct, 2014
1 commit
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A platform_driver does not need to set an owner, it will be populated by the
driver core.Signed-off-by: Wolfram Sang
14 Sep, 2014
2 commits
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This is just enough to let pm_clk_*() enable the functional clock, and
manage it for suspend/resume, if present.
Before, it was assumed enabled by the bootloader or reset state.To prevent the clock from being disabled while the module is needed for
wake-up, implement irq_chip.irq_set_wake(), which increments/decrements
the clock's enable_count when needed.Signed-off-by: Geert Uytterhoeven
Link: https://lkml.kernel.org/r/1410527720-18061-3-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper -
Signed-off-by: Geert Uytterhoeven
Link: https://lkml.kernel.org/r/1410527720-18061-2-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper
21 Aug, 2014
1 commit
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Set the ->irq_enable() and ->irq_disable() methods to NULL to enable
lazy disable of interrupts, and set IRQCHIP_MASK_ON_SUSPEND to tell the
core that only IRQs marked as wake-ups need to stay enabled during
suspend-to-RAM.This makes wake-up by gpio-keys from suspend-to-RAM work on
r8a7740/Armadillo.Signed-off-by: Geert Uytterhoeven
Link: https://lkml.kernel.org/r/1408546172-22484-1-git-send-email-geert+renesas@glider.be
Signed-off-by: Jason Cooper
24 Nov, 2013
1 commit
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The SENSE register bitfield position is incorrectly computed for SoCs
that use 2-bit IRQ sense fields. Fix it.This has been tested on the Marzen (H1) and Bockw (M1) boards.
This bug has been present since the renesas-intc-irqpin driver was
introduced by 443580486e3b9657 ("irqchip: Renesas INTC External IRQ pin
driver") in v3.10-rc1.Signed-off-by: Laurent Pinchart
Acked-by: Magnus Damm
Tested-by: Simon Horman
Signed-off-by: Simon Horman
19 Jun, 2013
1 commit
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To disable spurious interrupts, that get triggered on certain hardware, the
irqpin driver masks them on the parent interrupt controller. To specify
such broken devices a .control_parent parameter can be provided in the
platform data. In the DT case we need a property, to do the same.Signed-off-by: Guennadi Liakhovetski
Acked-by: Magnus Damm
Signed-off-by: Simon Horman
18 Jun, 2013
1 commit
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Most Renesas irqpin controllers have 4-bit sense fields, however, some
have different widths. This patch adds a DT binding to optionally
specify such non-standard values.Signed-off-by: Guennadi Liakhovetski
Acked-by: Arnd Bergmann
Signed-off-by: Simon Horman
28 Mar, 2013
1 commit
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On some hardware we don't have a 1-1 mapping from the external
interrupts coming from INTC to the GIC SPI pins. We can however
share lines to demux incoming IRQs on these SoCs.This patch enables the intc_irqpin driver to detect requests for shared
interrupt lines and demuxes them properly by querying the INTC INTREQx0A
registers.If you need multiple shared intc_irqpin device instances, be sure to mask
out all interrupts on the INTC that share the one line before you start
to register them. Else you run into IRQ floods that would be caused by
interrupts for which no handler has been set up yet when the first
intc_irqpin device is registered.Signed-off-by: Bastian Hecht
Acked-by: Magnus Damm
Signed-off-by: Simon Horman
18 Mar, 2013
6 commits
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Add initial DT support to the INTC External IRQ Pin
driver. At this point only hardware with 4-bit wide
sense registers is supported via DT.Signed-off-by: Magnus Damm
Signed-off-by: Simon Horman -
Use devm_kzalloc(), devm_ioremap_nocache()
and devm_request_irq() to simplify error
handling.Signed-off-by: Magnus Damm
Reviewed-by: Thomas Gleixner
Tested-by: Guennadi Liakhovetski
Signed-off-by: Simon Horman -
Add comments to describe the special case for
"force" versions of enable and disable functions.Signed-off-by: Magnus Damm
Reviewed-by: Thomas Gleixner
Tested-by: Guennadi Liakhovetski
Signed-off-by: Simon Horman -
Cache IRQ in domain_irq variable instead of
making use of irq_find_mapping(). While at it
rename the irq variable to requested_irq.Signed-off-by: Magnus Damm
Reviewed-by: Thomas Gleixner
Tested-by: Guennadi Liakhovetski
Signed-off-by: Simon Horman -
Remove whitespace damage and add newline
between variables and code.Signed-off-by: Magnus Damm
Reviewed-by: Thomas Gleixner
Tested-by: Guennadi Liakhovetski
Signed-off-by: Simon Horman -
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.The INTC hardware block usually contains a rather wide
range of features ranging from external IRQ pin handling
to legacy interrupt controller support. On older SoCs
the INTC is used as a general purpose interrupt controller
both for external IRQ pins and on-chip devices.On more recent ARM based SoCs with Cortex-A9 the main
interrupt controller is the GIC, but IRQ trigger setup
still need to happen in the INTC hardware block.This driver implements the glue code needed to configure
IRQ trigger and also handle mask/unmask and demux of
external IRQ pins hooked up from the INTC to the GIC.Tested on sh73a0 and r8a7779. The hardware varies quite
a bit with SoC model, for instance register width and
bitfield widths vary wildly. The driver requires one GIC
SPI per external IRQ pin to operate. Each driver instance
will handle up to 8 external IRQ pins.The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows configuration via platform data to support things
like static interrupt base address. DT support will
be added incrementally in the not so distant future.Signed-off-by: Magnus Damm
Acked-by: Thomas Gleixner
Signed-off-by: Simon Horman
