Eric Lee / smarc-fsl-linux-kernel

25 Jul, 2016

1 commit

  • 39f80bcb0   mmc: s3cmci: Register cpufreq notifier only on S3C24xx ... Browse Code »

    The driver registered for CPU frequency transitions to recalculate its
    clock when ARM clock frequency changes (ratio between frequencies of
    ARM's parent clock (fclk) and clock for peripherals remains fixed).

    This is needed only on S3C24xx platform when cpufreq driver is enabled
    so limit the ifdef to respective cpufreq Kconfig.

    Suggested-by: Marek Szyprowski
    Signed-off-by: Krzysztof Kozlowski
    Signed-off-by: Ulf Hansson

    Krzysztof Kozlowski
     

09 Jul, 2014

1 commit

02 Oct, 2009

3 commits

  • 68c5ed592   s3cmci: DMA fixes ... Browse Code »

    Fixes for the DMA transfer mode of the driver to try and improve the state
    of the code:

    - Ensure that dma_complete is set during the end of the command phase
    so that transfers do not stall awaiting the completion

    - Update the DMA debugging to provide a bit more useful information
    such as how many DMA descriptors where not processed and print the
    DMA addresses in hexadecimal.

    - Fix the DMA channel request code to actually request DMA for the
    S3CMCI block instead of whatever '0' signified.

    - Add fallback to PIO if we cannot get the DMA channel, as many of the
    devices with this block only have a limited number of DMA channels.

    - Only try and claim and free the DMA channel if we are trying to use it.

    This improves the driver DMA code to the point where it can now identify a
    card and read the partition table. However the DMA can still stall when
    trying to move data between the host and memory.

    Signed-off-by: Ben Dooks
    Cc:
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Ben Dooks
     
  • c22588937   s3cmci: add SDIO IRQ support ... Browse Code »

    The controller supports SDIO IRQ detection so add support for hardware
    assisted SDIO interrupt detection for the SDIO core. This improves the
    response time for SDIO interrupts and thus the transfer rate from devices
    such as the Marvel 8686.

    As a note, it does seem that the controller will miss an IRQ than is held
    asserted, so there are some manual checks to see if the SDIO interrupt is
    active after a transfer.

    Major testing on the S3C2440.

    Signed-off-by: Ben Dooks
    Cc:
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Ben Dooks
     
  • 9bdd203b4   s3cmci: add debugfs support for examining driver and hardware state ... Browse Code »

    Export driver state and hardware register state via debugfs entries
    created under a directory formed from dev_name() on the probed device when
    CONFIG_DEBUG_FS is set.

    Signed-off-by: Ben Dooks
    Cc:
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Ben Dooks
     

16 Oct, 2008

2 commits

  • 088a78af9   s3cmci: Support transfers which are not multiple of 32 bits. ... Browse Code »

    To be able to do SDIO the s3cmci driver has to support non-word-sized
    transfers. Change pio_words into pio_bytes and fix up all the places
    where it is used.

    This variant of the patch will not overrun the buffer when reading an
    odd number of bytes. When writing, this variant will still read past
    the end of the buffer, but since the driver can't support non-word-
    aligned transfers anyway, this should not be a problem, since a
    word-aligned transfer will never cross a page boundary.

    This has been tested with a CSR SDIO Bluetooth Type A device on a
    Samsung S3C24A0 processor.

    Signed-off-by: Christer Weinigel
    Signed-off-by: Ben Dooks
    Signed-off-by: Pierre Ossman

    Christer Weinigel
     
  • f87e6d00f   s3cmci: cpufreq support ... Browse Code »

    Support for cpu frequency changing.

    Signed-off-by: Ben Dooks
    Signed-off-by: Pierre Ossman

    ben@fluff.org.uk
     

15 Jul, 2008

2 commits