24 Jan, 2018
1 commit
11 Jan, 2018
1 commit
09 Jun, 2017
1 commit
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This patch removes the WARN_ONCE() test in spi_nor_write().
This macro triggers the display of a warning message almost every time we
use a UBI file-system because a write operation is performed at offset 64,
which is in the middle of the SPI NOR memory page. This is a valid
operation for ubifs.Hence this warning is pretty annoying and useless so we just remove it.
Signed-off-by: Cyrille Pitchen
Suggested-by: Richard Weinberger
Suggested-by: Andras Szemzo
Acked-by: Boris Brezillon
[Octavian: rebased to 4.9]
Signed-off-by: Octavian Purdila
Reviewed-by: "Frank Li"
08 Jun, 2017
5 commits
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Fix the logic error when reading dummy cycle for qspi ddr quad mode
Signed-off-by: Han Xu
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mtd->priv is no longer pointing to the struct nand_chip it is attached
to. Replace those accesses by mtd_to_nand() calls.Signed-off-by: Octavian Purdila
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ULP1 use new QSPI NOR chip MX25R6435F which is not in default id table.
Signed-off-by: Han Xu
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Since QSPI is not in A7 domain on i.MX7ULP, the clock framework doesn't
provide support to handle related clock, add QUIRK to indicate the QSPI
was handled by u-boot. May change the code after clock framework
supports M4 domain.Signed-off-by: Han Xu
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QSPI only support upto 16 LUT slots while the QSPI commands are more
than this number, reserve the last two slots for dynamic change (most
commands used in pairs). Later all extra supported commands will be add
in dynamic lut table.Signed-off-by: Han Xu
23 Feb, 2017
32 commits
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support QSPI on i.MX6ULL. By default, only QSPI1 was enabled, while
reworked board could support all 4 QSPI chips.Since i.MX6UL and i.MX6ULL QSPI controller are identical, reuse the
i.MX6UL datatype for i.MX6ULL.Signed-off-by: Han Xu
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support NAND on imx6ull
Signed-off-by: Han Xu
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missed the brackets for bch legacy support, which leads the large oob
nand bch setting to wrong path.Signed-off-by: Han Xu
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Provide an option in DT to use legacy bch geometry, which compatible
with the 3.10 kernel bch setting. To enable the feature, adding
"fsl,legacy-bch-geometry" under gpmi-nand node.NOTICE: The feature must be enabled/disabled in both u-boot and kernel.
Conflicts:
drivers/mtd/nand/gpmi-nand/gpmi-nand.hSigned-off-by: Han Xu
(cherry picked from commit 4d28b1693905526558892d40525763e6bc4469e4) -
fix the potential integer overflow issue found by coverify.
Signed-off-by: Han Xu
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For backward compatibility, kobs-ng need to know if the driver use
legacy raw mode or new bch layout raw mode, add a new flag in debugfs to
indicate the raw access mode.Signed-off-by: Han Xu
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support the bch layout with dedicate ecc for meta
Signed-off-by: Han Xu
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This reverts commit 76babd7d075c9c22a27e6bc272bb57b6327cfbd3.
Signed-off-by: Han Xu
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new implementation of GPMI NAND raw access functions was added in kernel
4.1 which changes the way from writing data in mirror mode to writing
data with BCH layout mode.New implementation can help third party tools to analysis the data since
all data were written in same layout, with or without ECC, but this
implementation doesn't work for NAND boot. Kobs-ng, the tool for NAND
boot will create the boot configuration data for each specific platform
and need to write the data to NAND in mirror mode. In this workaround,
we will keep using the previous raw NAND access function to fix the
issue.Signed-off-by: Han Xu
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check the return value to avoid the dereference null return value when
parsing device tree.Signed-off-by: Han Xu
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Fix the typo in when check bch geometry ecc chunk0 and chunkn size.
Signed-off-by: Fugang Duan
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For i.MX6UL and i.MX7D, ddr delay logic enable bit is changed from i.MX6SX.
If want to enable qspi ddr mode, ddr delay logic should be enabled.Signed-off-by: Peng Fan
(cherry picked and merge from commit f28986825a7be1cbf2b5103ea110db28c96e74c7)
Signed-off-by: Han XuConflicts:
drivers/mtd/spi-nor/fsl-quadspi.c -
add two more commands support for qspi on kernel 4.1, read EVCR and
write EVCR.Signed-off-by: Han Xu
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If the master mtd does not have any slave mtd partitions,
and its numeraseregions is one(only has one erease block), and
we attach the master mtd with : ubiattach -m 0 -d 0We will meet the error:
-------------------------------------------------------
root@freescale ~$ ubiattach /dev/ubi_ctrl -m 0 -d 0
UBI: attaching mtd0 to ubi0
UBI error: io_init: multiple regions, not implemented
ubiattach: error!: cannot attach mtd0
error 22 (Invalid argument)
-------------------------------------------------------In fact, if there is only one "erase block", we should not
prevent the attach.This patch fixes it.
Signed-off-by: Huang Shijie
(cherry picked from commit 361cdc47fc4c4db31c5485560cdabd94f409bd81)
(cherry picked from commit ebee7d74914fad3cf7223af84496811c9d2488a1) -
The LPSR turns off the power for IOMUX when suspending so restore the
IOMUX when resuming.Signed-off-by: Han Xu
(cherry picked from commit 906d0c1381e865dc7c96a4bde6fe694f1ce089a9) -
the obsolete bit DDR_EN on 6UL and 7D should be clear in case other
program set the bit and cause qspi probe fail.Signed-off-by: Han Xu
(cherry picked from commit d8b51cc358780f68e732522ee9bd6bd578dd6771) -
Enable DDR quad mode for Macronix qspi chip mx25l51245g by setting Quad
bit in status register and enabling in dts file.The LUT for SPINOR_OP_READ_1_4_4_D was initially designed for Spansion
qspi chip, so there is one cycle for "mode" after address and before
dummy. While Macronix qspi chip doesn't have this feature, so we just
take off one cycle in dts file to bypass this problem.Signed-off-by: Han Xu
(cherry picked and merge from commit e03fdad1c7713a7db70112e00c4ae96848accd34) -
Add a new entry for MX25L51245G QSPI NOR chip.
Signed-off-by: Han Xu
(cherry picked from commit 9f3f15ad1b0461d6b638c34599dd74d9c43fa01f) -
Since QSPI internal DDR sample point is relevant with board layout,
we can't use same value for all boards. Add ddrsmp parameter to device
tree for different i.MX6SX board.Signed-off-by: Ye.Li
(cherry picked and merge from commit c9115cc22d836b5b980ca20932a005ea61b20082)
(cherry picked from commit b0d9d9ce804247ccb2842bf53d2b32f14eed0309) -
i.MX6SX Sabreauto board enabled both NAND and QSPI1 drivrers, and by default,
NAND driver built first in kernel compiling, and it would be load first when
Kernel brought up.Since we could not guarantee all boards mounted NAND chips, we wish the Kernel
could load QSPI driver first, when system mapped QSPI and NAND, the mtd device
index won't change dynamically, otherwise, the mfgtool may write images to the
inappropriate storage devices.The code change moved the SPI driver at the prior position of NAND driver in
Makefile to solve this issue.Signed-off-by: Allen Xu
(cherry picked from commit 3d2d5724f7a2968b40c2ea0a70c09a3214da1496)
(cherry picked from commit b03ee70fdd1dfaa3be61817eb49d01d49cb107d3) -
This patch adds the DDR quad read flag for s25fl128s.
Signed-off-by: Huang Shijie
(cherry picked from commit 7346749f8f1083943431063bdd49ea9429a96941)
Signed-off-by: Han Xu -
Add DDR quad read opcode and LUT sequence for Micron N25Q256A.
Signed-off-by: Huang Shijie
(cherry picked from commit dc2a7430557dd3e102b56fdd6b6d0fe3b1e3e461) -
This patch adds the DDR(or DTR) quad read support for the Micron
SPI NOR flash.Signed-off-by: Han Xu
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The NOR flash can supports dual/quad/ddr-quad read.
Add more flags for these read transfers.From the datasheet, the chip support the 64K sector erase operation.
So remove the SECT_4K for the chip which makes the flash_erase faster.Signed-off-by: Han Xu
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Add the DDR quad read support for the fsl-quadspi driver.
Check the "spi-nor,ddr-quad-read-dummy" DT property, if the DT node is exit,
it means we could enable the DDR quad read.(1) Test this patch with imx6sx-sdb board (Spansion s25fl128s)
The clock rate is 66MHz.(2) The information of NOR flash:
-----------------------------------------------
root@imx6qdlsolo:~# mtdinfo /dev/mtd0
mtd0
Name: 21e4000.qspi
Type: nor
Eraseblock size: 65536 bytes, 64.0 KiB
Amount of eraseblocks: 256 (16777216 bytes, 16.0 MiB)
Minimum input/output unit size: 1 byte
Sub-page size: 1 byte
Character device major/minor: 90:0
Bad blocks are allowed: false
Device is writable: true
-----------------------------------------------(3) Test this patch set with UBIFS & bonnie++:
-----------------------------------------------
ubiattach /dev/ubi_ctrl -m 0
ubimkvol /dev/ubi0 -N test -m
mount -t ubifs ubi0:test tmp
bonnie++ -d tmp -u 0 -s 10 -r 5
-----------------------------------------------(4) Test this patch with mtd_speedtest.ko
root@imx6qdlsolo:~# insmod mtd_speedtest.ko dev=0
=================================================
mtd_speedtest: MTD device: 0
mtd_speedtest: not NAND flash, assume page size is 512 bytes.
mtd_speedtest: MTD device size 16777216, eraseblock size 65536, page size 512,
count of eraseblocks 256, pages per eraseblock 128, OOB size 0
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 665 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 49799 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 662 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 24236 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 657 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 32637 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 518 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 506 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 503 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 501 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 498 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 496 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 495 KiB/s
mtd_speedtest: finished
=================================================(5) Conclusion:
The DDR quad read could be 49799 KiB/s.Signed-off-by: Huang Shijie
Signed-off-by: Han Xu -
We can get the read/write/erase opcode from the spi nor framework now.
What's more is that we can get the correct dummy cycles.This patch uses the information stored in the spi_nor{} to remove the
hardcode in the fsl_qspi_init_lut().Signed-off-by: Huang Shijie
(cherry picked from commit 3a9f46be2a6d358924d69757858ec816764222d4) -
This patch adds the DDR quad read support by the following:
[1] add SPI_NOR_DDR_QUAD read mode.
[2] add DDR Quad read opcodes:
SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D[3] add set_ddr_quad_mode() to initialize for the DDR quad read.
Currently it only works for Spansion NOR.[3] about the dummy cycles.
We set the dummy with 8 for DDR quad read by default.
The m25p80.c can not support the DDR quad read, but the SPI NOR controller
can set the dummy value in its child DT node, and the SPI NOR framework
can parse it out.Signed-off-by: Han Xu
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add an empty sentinel entry to avoid the struct of_device_id is not
terminated with a NULL entry issue.Signed-off-by: Han Xu
(cherry picked from commit 2b1ce5ec442dde8801b6b2d059d22f5dce7c9c76) -
fix the bch setting issue when system suspend/resume, the bch geometry
only need to be saved to debugfs in driver initial stageSigned-off-by: Han Xu
(cherry picked from commit 3b4f7178854e428fb5ef08d554b13abe4f27c533) -
The erase threshold should be set to ecc_strength for these platforms.
Signed-off-by: Han Xu
(cherry picked from commit f46d113a02f5375c38fc9aba88c587fd672a30c4) -
The cod change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.Previous code has two methods for ECC layout setting, the
legacy_set_geometry and set_geometry_by_ecc_info, the difference
between these two methods is, legacy_set_geometry set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the set_geometry_by_ecc_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.2. If the oob is large or NAND required data chunk larger than oob size,
chose set_geometry_for_large_oob, otherwise use set_geometry_by_ecc_info3. legacy_set_geometry only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.Signed-off-by: Han Xu
(cherry picked from commit 78e8beff734adb72185405ae2cb55e0097eb96cb) -
save the bch layout setting in debugfs for the upper layer applications,
such as kobs-ng.Signed-off-by: Han Xu
(cherry picked from commit 8a373e796c21f4e9b714039e5f0b7d9388ef5a32)
