23 Feb, 2017
22 commits
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We should do bitwise OR operation for all valid irq enable bits to
get the full irq mask. So, to take the bit4(HANDSHAKE_ERROR_IRQ_EN)
into calculation, the mask should be 0x1f instead of 0xf.Reported-by: Asim Zaidi
Signed-off-by: Liu Ying -
We've got more than 24 channels defined in ipu_channel_t, which causes
potential overrun on array ipu->sec_chan_en and ipu->thrd_chan_en.
This patch enlarges the array size to IPU_MAX_CH(32) to fix this issue.This issue is reported by Coverity:
Out-of-bounds read (OVERRUN)
overrun-local: Overrunning array ipu->sec_chan_en of 24 bytes at byte offset
25 using index channel >> 24 (which evaluates to 25).
if ((ipu->sec_chan_en[IPU_CHAN_ID(channel)]) &&
((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
(channel == MEM_VDI_PRP_VF_MEM))) {Out-of-bounds read (OVERRUN)
overrun-local: Overrunning array ipu->thrd_chan_en of 24 bytes at byte offset
25 using index channel >> 24 (which evaluates to 25).
if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);Signed-off-by: Liu Ying
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This patch removes boilerplate code to register clocks for two DIs of one IPU.
Also, the char strings for storing the pixel clock parent names are wrongly
placed in the kernel rodata section, which will be overwritten when clocks
are registered. This patch moves the problematic strings to stack. Since
clk_register() will cache his own version from non-kernel-rodata space, this
may fix the issue.Signed-off-by: Liu Ying
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The register IPU_CONF contains several dedicated enable bits for IPU internal
modules. When we enable an IPU logic channel, e.g., MEM_BG_SYNC, by calling
the function ipu_enable_channel(), we should enable the necessary IPU internal
modules for that logic channel instead of touching other irrelevant modules.
This may most definitely keep the steps for enabling a logic channel steady
if no IPU internal module is shared by different logic channels.An known issue is caused by breaking this rule: we are likely to switch the
display pixel clock source from IPU internal HSP clock to external clock when
enabling a display which is driven by MEM_BG_SYNC. This operation is safe if
the relevant DI enable bit in IPU_CONF is zero. In case another task, e.g.,
MEM_PP_MEM, is being enabled in parallel, it may accidently set the DI enable
bit to one before the pixel clock source is switched, which may cause the
display engine malfunction. To fix this issue, this patch configures the
register IPU_CONF correctly in the function ipu_enable_channel() according to
specific IPU logic channels.Signed-off-by: Liu Ying
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This patch adds missing parentheses around the argument of the macro
WROD to avoid any potential macro expansion issue.Signed-off-by: Liu Ying
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This patch adds missing parentheses around the arguments of the macro
ipu_ch_param_addr/ipu_ch_param_set_field(_io)/ipu_ch_param_mod_field(_io)/
ipu_ch_param_read_field(_io) to avoid any potential macro expansion issue.Signed-off-by: Liu Ying
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This patch adds missing parentheses around the argument of the macro
idma_is_valid and idma_mask to avoid any potential macro expansion issue.Signed-off-by: Liu Ying
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The local variable div_ratio could be less than zero, so let's define
it as type of int32_t instead of uint32_t.This issue is reported by Coverity:
Unsigned compared against 0 (NO_EFFECT)
unsigned_compare: This less-than-zero comparison of an unsigned value
is never true. div_ratio < 0U.
if (div_ratio > 0xFF || div_ratio < 0) {
dev_dbg(ipu->dev, "value of pixel_clk extends normal range\n");
return -EINVAL;
}Signed-off-by: Liu Ying
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This patch converts macro tri_cur_buf_mask/shift to function to address the
following issue reported by Coverity:
Operands don't affect result (CONSTANT_EXPRESSION_RESULT)
result_independent_of_operands: dma_chan * 2 != 63 is always true regardless of
the values of its operands. This occurs as the logical first operand of '?:'.Signed-off-by: Liu Ying
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A minor improvement for _ipu_is_smfc_chan() to address the following
issue reported by Coverity:
Unsigned compared against 0 (NO_EFFECT)
unsigned_compare: This greater-than-or-equal-to-zero comparison of an
unsigned value is always true. dma_chan >= 0U.
return ((dma_chan >= 0) && (dma_chan -
This patch fixes the following issue reported by Coverity:
if (IS_ERR(clk))
freed_arg: kfree frees clk. [Note: The source code implementation of the
function has been overridden by a builtin model.]
kfree(clk);Use after free (USE_AFTER_FREE)
use_after_free: Using freed pointer clk.
return clk;Signed-off-by: Liu Ying
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This patch fixes the following issue reported by Coverity:
if (IS_ERR(clk))
freed_arg: kfree frees clk. [Note: The source code implementation of the
function has been overridden by a builtin model.]
kfree(clk);Use after free (USE_AFTER_FREE)
use_after_free: Using freed pointer clk.
return clk;Signed-off-by: Liu Ying
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This patch fixes the following issue reported by Coverity:
Constant expression result (CONSTANT_EXPRESSION_RESULT)
always_true_or: The "or" condition disp != 0 || disp != 1 will always be true
because disp cannot be equal to two different values at the same time, so it
must be not equal to at least one of them.
if ((disp != 0) || (disp != 1))
return;Signed-off-by: Liu Ying
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We should do the bailout dance correctly for the ioctrl IPU_ALLOC:
- Free the mem pointer.
- Free the DMA.
- Delete the mem->list from the ipu_alloc_list.The potential memory leakage issue on the mem pointer is reported by Coverity:
if (get_user(size, argp))
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable mem going out of scope leaks the storage it points to.
return -EFAULT;Signed-off-by: Liu Ying
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The pre_list can be accessed in an irq context. To avoid potential hang up
issue, use spinlock to protect pre_list instead of mutex.Signed-off-by: Liu Ying
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In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.In non-small y resolution cases(>9 lines), we choose to check the STORE_BLOCK_Y
field of the register HW_PRE_STRORE_ENGINE_STATUS to determine the bad window
to update the SDW_UDPATE bit of the PRE_CTRL register. According to the
description of the STRORE_BLOCK_Y field in block mode, the field indicates the
Y coordinate of the block currently being rendered. Thus, we should round up
the real display y resolution to 4 lines to align with the block high(the out-
standing lines are cropped by PRG and IPU). To maximize the safe window, we
just need to avoid updating the shadow bit during the last block of lines.
To conclude, the bad window for block mode is (store_block_y == 0 ||
store_block_y >= DIV_ROUND_UP(y_resolution, 4) - 1).Signed-off-by: Liu Ying
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In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.The software mechanism to set the PRE_CTRL register is different for PRE Y
resolution higher than 9 lines and lower than or equal to 9 lines.For cases in which Y resolution is higher than 9 lines, before we update PRE
shadow, we just need to wait until the PRE store engine status runs out of
the problematic PRE automatic writing window.While for cases in which Y resolutin is lower than or equal to 9 lines, we
have to update PRE shadow in the buffer flip interrupt handler.Signed-off-by: Liu Ying
(cherry picked from commit bd9c14e24aaf67926dfd31bd819ab0c87129fe4b) -
In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.This patch exports a function to set the PRE_CTRL register so that it could be
used by the software when the PRE automatic writing doesn't happen for sure.Signed-off-by: Liu Ying
(cherry picked from commit e64bbcd9243a17f9eba9cb3abb6f2c1939eae110) -
LVDS0 can not work on imx6q auto and SDB board,
it is caused by ldb0 clock setting is missed in ipu driver.Signed-off-by: Sandor Yu
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Fix buiulding warning:
drivers/mxc/ipu3/ipu_disp.c:435:29: warning: initialization discards
'const' qualifier from pointer target type
[-Wdiscarded-array-qualifiers]
{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0},
{DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG,
&rgb2ycbcr_coeff} },Signed-off-by: Sandor Yu
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4.1 kernel apply the followed patch:
commit 73e0e496afdac9a5190eb3b9c51fdfebcc14ebd4
clkdev: Always allocate a struct clk and call __clk_get() w/ CCFclock_get will return a new struct clk, so we can't use the pointer
of clk struct to compare clk whether is equal, replace with clk name.Signed-off-by: Sandor Yu
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Forward imx_3.14.y IPU and display drivers to 4.1 kernel.
This includes IPU core driver, display driver, LDB and HDMI driver.Signed-off-by: Sandor Yu
