21 Sep, 2016
1 commit
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As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin
Reviewed-by: Andrew Lunn
Acked-by: Rob Herring
Acked-by: Linus Walleij
Signed-off-by: Gregory CLEMENT
24 Jul, 2016
1 commit
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On Marvell mv88f6180 with pin control driver one can not use multi
purpose pins 35 through 44.
I'm using this controller on an embedded board and i found that the
pin multiplexing is not the same as in the hardware spezification.
This patch alters the pin description so that mpp pins 0 to 19 as well
as 35 to 44 are usable.Pin settings i used can be found here:
http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdfSigned-off-by: Andreas Klinger
Reviewed-by: Sebastian Hesselbarth
Signed-off-by: Linus Walleij
21 Apr, 2016
1 commit
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Use devm_pinctrl_register() for pin control registration and remove
need of .remove callback.Signed-off-by: Laxman Dewangan
Cc: Thomas Petazzoni
Cc: Hongzhou Yang
Cc: Fabian Frederick
Cc: Andrew Andrianov
Reviewed-by: Thomas Petazzoni
Signed-off-by: Linus Walleij
14 Feb, 2016
1 commit
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When assigning mpp settings from static mpp modes to mpp groups,
we do not want any groups that have no supported setting for a
specific Kirkwood variant. However, when there is at least a
single supported setting, we need to assign the number of all
settings in this mode to grp->num_settings as we are reusing
the static modes table.Fixes: 0581b16b1840 ("pinctrl: mvebu: complain about missing group after checking variant")
Reported-by: Aaro Koskinen
Tested-by: Aaro Koskinen
Cc: Gregory Clement
Cc: Andrew Lunn
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Sebastian Hesselbarth
Signed-off-by: Linus Walleij
09 Dec, 2015
1 commit
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Common MVEBU pinctrl driver core gets an array of controls to modify
a specific set of registers and an array of modes for each pingroup
from each of the different SoC families of MVEBU.Some SoC families comprise different variants that differ in available
pingroups and also controls, but to ease driver development, we can
pass a variant mask to disable specific pingroups for some variants.
However, controls are limited to the true number of pinctrl groups
avaiable on a variant.Now, when pinctrl core driver parses over above arrays, it tries to
match modes with available controls and complains about missing
controls for modes that are passed to the core but actually are not
avaiable on a variant with:kirkwood-pinctrl f1010000.pin-controller: unknown pinctrl group 36
This warning is a false-positive and annoying, so move the warning
after we checked the variant mask for each mode setting. Also, if
there is no supported setting for this variant, do not complain at
all.Signed-off-by: Sebastian Hesselbarth
Reported-by: Linus Walleij
Signed-off-by: Linus Walleij
01 Dec, 2015
1 commit
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CONFIG_PINCTRL_MVEBU is more suitable than CONFIG_PLAT_ORION
to guard the drivers/pinctrl/mvebu/ directory.Signed-off-by: Masahiro Yamada
Signed-off-by: Linus Walleij
25 Jun, 2015
1 commit
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Pull pin control updates from Linus Walleij:
"Here is the bulk of pin control changes for the v4.2 series: Quite a
lot of new SoC subdrivers and two new main drivers this time, apart
from that business as usual.Details:
Core functionality:
- Enable exclusive pin ownership: it is possible to flag a pin
controller so that GPIO and other functions cannot use a single pin
simultaneously.New drivers:
- NXP LPC18xx System Control Unit pin controller
- Imagination Pistachio SoC pin controllerNew subdrivers:
- Freescale i.MX7d SoC
- Intel Sunrisepoint-H PCH
- Renesas PFC R8A7793
- Renesas PFC R8A7794
- Mediatek MT6397, MT8127
- SiRF Atlas 7
- Allwinner A33
- Qualcomm MSM8660
- Marvell Armada 395
- Rockchip RK3368Cleanups:
- A big cleanup of the Marvell MVEBU driver rectifying it to
correspond to reality
- Drop platform device probing from the SH PFC driver, we are now a
DT only shop for SuperH
- Drop obsolte multi-platform check for SH PFC
- Various janitorial: constification, grammar etcImprovements:
- The AT91 GPIO portions now supports the set_multiple() feature
- Split out SPI pins on the Xilinx Zynq
- Support DTs without specific function nodes in the i.MX driver"* tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
pinctrl: rockchip: add support for the rk3368
pinctrl: rockchip: generalize perpin driver-strength setting
pinctrl: sh-pfc: r8a7794: add SDHI pin groups
pinctrl: sh-pfc: r8a7794: add MMCIF pin groups
pinctrl: sh-pfc: add R8A7794 PFC support
pinctrl: make pinctrl_register() return proper error code
pinctrl: mvebu: armada-39x: add support for Armada 395 variant
pinctrl: mvebu: armada-39x: add missing SATA functions
pinctrl: mvebu: armada-39x: add missing PCIe functions
pinctrl: mvebu: armada-38x: add ptp functions
pinctrl: mvebu: armada-38x: add ua1 functions
pinctrl: mvebu: armada-38x: add nand functions
pinctrl: mvebu: armada-38x: add sata functions
pinctrl: mvebu: armada-xp: add dram functions
pinctrl: mvebu: armada-xp: add nand rb function
pinctrl: mvebu: armada-xp: add spi1 function
pinctrl: mvebu: armada-39x: normalize ref clock naming
pinctrl: mvebu: armada-xp: rename spi to spi0
pinctrl: mvebu: armada-370: align spi1 clock pin naming
pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
...
10 Jun, 2015
33 commits
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Currently, pinctrl_register() just returns NULL on error, so the
callers can not know the exact reason of the failure.Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some
-ENOMEM on error of pinctrl_register(), although the error code
might be different from the real cause of the error.This commit reworks pinctrl_register() to return the appropriate
error code and modifies all of the pinctrl drivers to use IS_ERR()
for the error checking and PTR_ERR() for getting the error code.Signed-off-by: Masahiro Yamada
Acked-by: Patrice Chotard
Acked-by: Thierry Reding
Acked-by: Heiko Stuebner
Tested-by: Mika Westerberg
Acked-by: Mika Westerberg
Acked-by: Lee Jones
Acked-by: Sören Brinkmann
Acked-by: Laurent Pinchart
Acked-by: Ray Jui
Acked-by: Antoine Tenart
Acked-by: Hongzhou Yang
Acked-by: Wei Chen
Signed-off-by: Linus Walleij -
The Armada 39x SoC family has grown a new variant, the Armada 395,
which sits between the Armada 390 and Armada 398 in terms of
features. This commit adds support for this additional variant to the
Armada 39x pinctrl driver.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest version of the Armada 39x datasheet documents several new
SATA related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 39x pinctrl driver as
well as to its DT binding documentation.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest version of the Armada 39x datasheet documents several new
PCIe related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 39x pinctrl driver as
well as to its DT binding documentation.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest version of the Armada 38x datasheet documents several new
PTP related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest version of the Armada 38x datasheet documents several new
UART1 related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest version of the Armada 38x datasheet documents several new
NAND related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest version of the Armada 38x datasheet documents several new
SATA related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest Armada XP datasheet documents several new DRAM related
functions on various MPPs. This commit adds the description of these
new functions in the Armada XP pinctrl driver and its DT binding
documentation.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest version of the Armada XP datasheet documents a new
NAND-related MPP function on MPP48, for which this commit adds
support.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The latest Armada XP datasheet documents that some of the MPP pins can
be used to access the second SPI bus, labelled 'spi1'. This commit
adds the corresponding pins in the pinctrl driver and its DT binding
documentation.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
This commit normalizes the subnames of the reference clock MPP pins in
the Armada 39x pinctrl driver to match with the name used on other
SoCs.Since only the subnames are changed, DT backward compatibility is not
affected.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
After updating to the latest Armada XP datasheet, we discovered that
there is a second SPI bus accessible from the MPP pins, called 'spi1'.In order to be consistent with other SoCs having two SPI busses, this
commit renames the functions of the first SPI bus to 'spi0' instead of
just 'spi'.This commit obviously breaks the DT backward compatibility for the
people using the "spi" function name in their Device Tree.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the
'sck' subname and not 'clk', so this commit adjusts the code and
documentation accordingly.Since this commit only changes the subname, DT backward compatibility
is not affected.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
For consistency with the datasheet, this commit renames the VDD
function of the MPP4 pin.While this changes the DT compatibility, it is not considered to be a
problem since this pin is unlikely to be used for anything but
debugging purposes.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
This commit normalizes the naming of the Ethernet txclkout pin to be
the same accross Marvell SoCs. It is worth mentioning that the DT
binding documentation of the Armada XP was wrong for MPP12: it said
the function was ge1(txd0), while it is in fact ge1(txclkout). It is
however not really a fix worth sending to stable since it does not
change the behavior, and the driver itself was correct.Since only the subnames are changed, DT backward compatibility is not
affected.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
This commit aligns the naming of the audio 'lrclk' pin accross Marvell
SoCs.Since only the subname is changed, the DT backward compatibility is
not affected.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
This commit normalizes the naming of PCIe pins to use 'rstout' instead
of 'rstoutn' or 'rst-out'.Since only the subnames are changed, DT compatibility is not affected.
Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
This commit normalizes the naming of the TDM pins accross the
different Marvell SoCs. Mainly it consists in:* Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn'
becomes 'rst'* Renaming the main name 'tdm2c' to 'tdm' on Armada 38x.
* Change the main name 'tdm-1' to 'tdm' for one of the pins of the
Armada XPThe last two changes affect DT compatibility, but since the TDM
interface is nowhere near being supported in mainline, it should not
be considered to be a serious problem at this point.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
All SoCs use "nand" to designate NAND pins, only Armada 39x is using
"nd", which is not consistent. This commit fixes that by renaming the
corresponding functions.It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the
convention used everywhere that we don't encode the 'n' part of signal
names.While this commit changes the main name of function, therefore
potentially breaking the DT compatibility, this is not a problem since
Armada 39x is a brand new SoC which isn't used in production yet.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
This commit modifies the definition of the Device Bus interface pins
to be consistent accross SoCs. Especially, it removes the 'n'
indicators that we don't encode in the subnames of pins:'dev(wen0)' becomes 'dev(we0)'
'dev(wen1)' becomes 'dev(we1)'
'dev(oen)' becomes 'dev(oe)'
etc.In addition, it fixes the Armada 375 DT binding documentation, which
forgot to document the 'dev' function for MPP46, MPP57 and MPP63.Since only the subnames are changed, this commit does not affect DT
compatibility.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
In order to be consistent with the datasheet and some other SoCs, this
commit renames the SDIO pins of the Armada 39x from "sd" to "sd0".While this changes the DT binding, this is not a problem since Armada
39x is a brand new SoC which isn't used in production yet (so now is
the right time to fix such things).Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
This commit makes the naming of SATA related MPP functions consistent
accross SoCs by adjusting the Armada 39x definition to use "prsnt"
instead of "present".Since only the subnames are changed, the DT binding is not modified at
all.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
This commit makes the dram functions naming (both the name and
subname) consistent accross SoC, by using:dram(vttctrl)
dram(deccerr)in all Marvell SoCs.
Due to the change to the name, it changes the DT binding, but these
functions are not used by any in-tree Device Tree file, and are very
unlikely to be used by anyone.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The subnames are purely informative, but it's nicer when they match
accross SoCs. This commit adjusts the Armada 375, Armada 38x and
Armada 39x MPP definitions so that the subnames of the PTP pins match
the ones used on Armada XP and Kirkwood.Signed-off-by: Thomas Petazzoni
Signed-off-by: Linus Walleij -
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and
a second one of 27 GPIOs. However, since there is a total of 60 MPP
pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.Signed-off-by: Thomas Petazzoni
Cc: # v4.1+
Fixes: ee086577abe7f ("pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x")
Signed-off-by: Linus Walleij -
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and
a second one of 27 GPIOs. However, since there is a total of 60 MPP
pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.Signed-off-by: Thomas Petazzoni
Cc: # v3.15+
Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385")
Signed-off-by: Linus Walleij -
There was an incorrect space in the definition of the function of one
pin in the Armada 375 pinctrl driver, which this commit fixes.Signed-off-by: Thomas Petazzoni
Cc: # v3.15+
Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij -
There was a mistake in the definition of the functions for MPP48 on
Marvell Armada XP. The second function is dev(clkout), and not tclk.Signed-off-by: Thomas Petazzoni
Cc: # v3.7+
Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij -
The latest version of the Armada XP datasheet no longer documents the
VDD cpu_pd functions, which might indicate they are not working and/or
not supported. This commit ensures the pinctrl driver matches the
datasheet.Signed-off-by: Thomas Petazzoni
Cc: # v3.7+
Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij -
After updating to a more recent version of the Armada XP datasheet, we
realized that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.Signed-off-by: Thomas Petazzoni
Cc: # v3.7+
Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij -
After updating to a more recent version of the Armada 375, we realized
that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.Signed-off-by: Thomas Petazzoni
Cc: # v3.15+
Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij -
Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly
named "spi0-1" instead of just "spi0". This commit fixes that.This DT binding change does not affect any of the in-tree users.
Signed-off-by: Thomas Petazzoni
Cc: # v3.7+
Fixes: 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370")
Signed-off-by: Linus Walleij
