07 Jan, 2016
1 commit
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Add SGPIO support to Marvell 94xx.
Signed-off-by: Wilfried Weissmann
Reviewed-by: James Bottomley
Signed-off-by: Martin K. Petersen
20 Jun, 2014
1 commit
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The direct cause is IRQ_SPI is already defined as a macro in unicore32
architecture (also, blackfin and mips architectures define it). The
related error (unicore32 with allmodconfig)CC [M] drivers/scsi/mvsas/mv_94xx.o
In file included from drivers/scsi/mvsas/mv_94xx.c:27:
drivers/scsi/mvsas/mv_94xx.h:176: error: expected identifier before numeric constantAnd IRQ_SAS_A and IRQ_SAS_B are used as 'u32' (although "enum
pci_interrupt_cause" is not used directly, now).All together, need add 'MVS_' for "enum pci_interrupt_cause".
Signed-off-by: Chen Gang
Reviewed-by: Christoph Hellwig
Reviewed-by: Xuetao Guan
Signed-off-by: Xuetao Guan
30 Nov, 2012
1 commit
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The macro bit(n) is defined as ((u32)1 << n), and thus it doesn't work
with n >= 32, such as in mvs_94xx_assign_reg_set():if (i >= 32) {
mvi->sata_reg_set |= bit(i);
...
}The shift ((u32)1 << n) with n >= 32 also leads to undefined behavior.
The result varies depending on the architecture.This patch changes bit(n) to do a 64-bit shift. It also simplifies
mv_ffc64() using __ffs64(), since invoking ffz() with ~0 is undefined.Signed-off-by: Xi Wang
Acked-by: Xiangliang Yu
Cc: stable@vger.kernel.org
Signed-off-by: James Bottomley
26 Jul, 2011
5 commits
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Remove obsolete comments and add new comments
Signed-off-by: Xiangliang Yu
Signed-off-by: James Bottomley -
Change code to match HBA datasheet.
Change code to make it readable.
Add support big endian for mvs_prd_imt.
Add cpu_to_le32 and cpu_to_le64 to use on addr.
Add scan_finished for structure mvs_prv_info.Signed-off-by: Xiangliang Yu
Signed-off-by: James Bottomley -
Add new macros: MVS_SOFT_RESET, MVS_HARD_RESET, MVS_PHY_TUNE,
MVS_COMMAND_ACTIVE, EXP_BRCT_CHG, MVS_MAX_SG
Add new member sg_width in struct mvs_chip_info
Use macros rather than magic number
Add new functions: mvs_fill_ssp_resp_iu, mvs_set_sense,
mvs_94xx_clear_srs_irq, mvs_94xx_phy_set_link_rateSigned-off-by: Xiangliang Yu
Signed-off-by: James Bottomley -
Remove unused macros: VSR_PHY_VS0, VSR_PHY_VS1, MVS_SLOTS,
MVS_CAN_QUEUE, MVS_MSI, SG_MX, _MV_DUMP, MV_DISABLE_NCQ
Remove unused variables for mvs_info: irq, exp_req, cmd_size
Remove unused functions: mvs_get_sas_addr, mvs_hexdump,
mvs_hba_sb_dump, mvs_hab_memory_dump, mvs_hba_cq_dumpSigned-off-by: Xiangliang Yu
Signed-off-by: James Bottomley -
Add 94xx phy tuning to aid manufacturing.
Add support for 94xx multiple revisions: A0, B0, C0, C1, C2.Signed-off-by: Xiangliang Yu
Signed-off-by: James Bottomley
02 May, 2011
1 commit
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1. Add support for Task collector mode.
2. Fixed relative collector mode bug:
- I/O failed when disks is on two ports
- system hang when hotplug disk
- system hang when unplug disk during run IO
3. Unlock ap->lock within .lldd_execute_task for direct mode to
improve performanceSigned-off-by: Xiangliang Yu
Signed-off-by: James Bottomley
21 May, 2009
1 commit
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This version contains following main changes
- Switch to new layout to support more types of ASIC.
- SSP TMF supported and related Error Handing enhanced.
- Support flash feature with delay 2*HZ when PHY changed.
- Support Marvell 94xx series ASIC for 6G SAS/SATA, which has 2
88SE64xx chips but any different register description.
- Support SPI flash for HBA-related configuration info.
- Other patch enhanced from kernel side such as increasing PHY type[jejb: fold back in DMA_BIT_MASK changes]
Signed-off-by: Ying Chu
Signed-off-by: Andy Yan
Signed-off-by: Ke Wei
Signed-off-by: Jeff Garzik
Signed-off-by: James Bottomley
