03 Dec, 2015

1 commit

• cdd5de500   soc: ti: Add wkup_m3_ipc driver ... Browse Code »

  Introduce a wkup_m3_ipc driver to handle communication between the MPU
  and Cortex M3 wkup_m3 present on am335x.

  This driver is responsible for actually booting the wkup_m3_rproc and
  also handling all IPC which is done using the IPC registers in the control
  module, a mailbox, and a separate interrupt back from the wkup_m3. A small
  API is exposed for executing specific power commands, which include
  configuring for low power mode, request a transition to a low power mode,
  and status info on a previous transition.

  Signed-off-by: Dave Gerlach
  Signed-off-by: Tony Lindgren

  Dave Gerlach

  2015-12-03 23:24:29 +0800  

30 Jan, 2015

1 commit

• df351f1ef   soc: ti: knav_qmss_queue: makefile tweak to build as dynamic module ... Browse Code »

  Currently configuring qmss and dma as dynamic module creates three .ko
  files. knav_qmss_acc.ko and knav_qmss_queue.ko both can't be insmod
  because of circular dependency. So combine these two into one module
  by changing the makefile.

  Signed-off-by: Murali Karicheri
  Signed-off-by: Santosh Shilimkar

  Murali Karicheri

  2015-01-30 05:23:51 +0800  

24 Sep, 2014

2 commits

• 88139ed03   soc: ti: add Keystone Navigator DMA support ... Browse Code »

  The Keystone Navigator DMA driver sets up the dma channels and flows for
  the QMSS(Queue Manager SubSystem) who triggers the actual data movements
  across clients using destination queues. Every client modules like
  NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO
  Engines has its own instance of packet dma hardware. QMSS has also
  an internal packet DMA module which is used as an infrastructure
  DMA with zero copy.

  Initially this driver was proposed as DMA engine driver but since the
  hardware is not typical DMA engine and hence doesn't comply with typical
  DMA engine driver needs, that approach was naked. Link to that
  discussion -
  https://lkml.org/lkml/2014/3/18/340

  As aligned, now we pair the Navigator DMA with its companion Navigator
  QMSS subsystem driver.

  Cc: Greg Kroah-Hartman
  Cc: Kumar Gala
  Cc: Olof Johansson
  Cc: Arnd Bergmann
  Cc: Grant Likely
  Cc: Rob Herring
  Cc: Mark Rutland
  Signed-off-by: Sandeep Nair
  Signed-off-by: Santosh Shilimkar

  Santosh Shilimkar

  2014-09-24 21:49:15 +0800  
• 41f93af90   soc: ti: add Keystone Navigator QMSS driver ... Browse Code »

  The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
  the main hardware sub system which forms the backbone of the Keystone
  Multi-core Navigator. QMSS consist of queue managers, packed-data structure
  processors(PDSP), linking RAM, descriptor pools and infrastructure
  Packet DMA.

  The Queue Manager is a hardware module that is responsible for accelerating
  management of the packet queues. Packets are queued/de-queued by writing or
  reading descriptor address to a particular memory mapped location. The PDSPs
  perform QMSS related functions like accumulation, QoS, or event management.
  Linking RAM registers are used to link the descriptors which are stored in
  descriptor RAM. Descriptor RAM is configurable as internal or external memory.

  The QMSS driver manages the PDSP setups, linking RAM regions,
  queue pool management (allocation, push, pop and notify) and descriptor
  pool management. The specifics on the device tree bindings for
  QMSS can be found in:
  Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt

  Cc: Greg Kroah-Hartman
  Cc: Kumar Gala
  Cc: Olof Johansson
  Cc: Arnd Bergmann
  Cc: Grant Likely
  Cc: Rob Herring
  Cc: Mark Rutland
  Signed-off-by: Sandeep Nair
  Signed-off-by: Santosh Shilimkar

  Sandeep Nair

  2014-09-24 21:49:14 +0800