27 Sep, 2016

1 commit

01 May, 2016

1 commit

  • The variable p is a data structure which is used by the driver core
    internally and it is not expected that busses will be directly accessing
    these driver core internal only data.

    Signed-off-by: Sudip Mukherjee
    Signed-off-by: Greg Kroah-Hartman

    Sudip Mukherjee

09 Feb, 2016

1 commit

  • Add support for more than 128 peripherals by taking a lazy
    caching approach to the mapping tables. Instead of reading and
    caching the tables at boot given some fixed size, read them and
    cache them on an as needed basis. We still assume a max size of
    512 peripherals, trading off some space for simplicity.

    Based on a patch by Gilad Avidov and
    Sagar Dharia .

    Cc: Gilad Avidov
    Cc: Sagar Dharia
    Signed-off-by: Stephen Boyd
    Signed-off-by: Greg Kroah-Hartman

    Stephen Boyd

05 Nov, 2015

1 commit

  • Pull char/misc driver updates from Greg KH:
    "Here is the big char/misc driver update for 4.4-rc1. Lots of
    different driver and subsystem updates, hwtracing being the largest
    with the addition of some new platforms that are now supported. Full
    details in the shortlog.

    All of these have been in linux-next for a long time with no reported

    * tag 'char-misc-4.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (181 commits)
    fpga: socfpga: Fix check of return value of devm_request_irq
    lkdtm: fix ACCESS_USERSPACE test
    mcb: Destroy IDA on module unload
    mcb: Do not return zero on error path in mcb_pci_probe()
    mei: bus: set the device name before running fixup
    mei: bus: use correct lock ordering
    mei: Fix debugfs filename in error output
    char: ipmi: ipmi_ssif: Replace timeval with timespec64
    fpga: zynq-fpga: Fix issue with drvdata being overwritten.
    fpga manager: remove unnecessary null pointer checks
    fpga manager: ensure lifetime with of_fpga_mgr_get
    fpga: zynq-fpga: Change fw format to handle bin instead of bit.
    fpga: zynq-fpga: Fix unbalanced clock handling
    misc: sram: partition base address belongs to __iomem space
    coresight: etm3x: adding documentation for sysFS's cpu interface
    vme: 8-bit status/id takes 256 values, not 255
    fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000
    ARM: zynq: dt: Updated devicetree for Zynq 7000 platform.
    ARM: dt: fpga: Added binding docs for Xilinx Zynq FPGA manager.
    ver_linux: proc/modules, limit text processing to 'sed'

    Linus Torvalds

14 Oct, 2015

1 commit

  • The struct irq_domain contains a "struct device_node *" field
    (of_node) that is almost the only link between the irqdomain
    and the device tree infrastructure.

    In order to prepare for the removal of that field, convert all
    users to use irq_domain_get_of_node() instead.

    Signed-off-by: Marc Zyngier
    Reviewed-and-tested-by: Hanjun Guo
    Tested-by: Lorenzo Pieralisi
    Cc: Tomasz Nowicki
    Cc: Suravee Suthikulpanit
    Cc: Graeme Gregory
    Cc: Jake Oshins
    Cc: Jiang Liu
    Cc: Jason Cooper
    Cc: Rafael J. Wysocki
    Link: http://lkml.kernel.org/r/1444737105-31573-2-git-send-email-marc.zyngier@arm.com
    Signed-off-by: Thomas Gleixner

    Marc Zyngier

04 Oct, 2015

2 commits

  • Silences this static checker warning:

    pmic_arb_write_cmd() warn: always true condition
    '(opc (0-255
    Signed-off-by: Stephen Boyd
    Reviewed-by: Bjorn Andersson
    Signed-off-by: Greg Kroah-Hartman

    Stephen Boyd
  • We don't want to swap bytes that we're reading and writing to the
    FIFOs when we're running on a big-endian CPU. Doing so causes
    problems like where the qcom-spmi-iadc driver can't detect the
    type of device because the bytes are all mixed up. Use the raw IO
    accessors for these API instead, and collapse pmic_arb_base_read()
    into the byte reading API so that we aren't tempted to read non-FIFO
    data like commands with that function.

    Cc: Andy Gross
    Signed-off-by: Stephen Boyd
    Acked-by: Bjorn Andersson
    Signed-off-by: Greg Kroah-Hartman

    Stephen Boyd

21 Sep, 2015

1 commit

16 Sep, 2015

1 commit

  • Most interrupt flow handlers do not use the irq argument. Those few
    which use it can retrieve the irq number from the irq descriptor.

    Remove the argument.

    Search and replace was done with coccinelle and some extra helper
    scripts around it. Thanks to Julia for her help!

    Signed-off-by: Thomas Gleixner
    Cc: Julia Lawall
    Cc: Jiang Liu

    Thomas Gleixner

02 Sep, 2015

1 commit

  • Pull irq updates from Thomas Gleixner:
    "This updated pull request does not contain the last few GIC related
    patches which were reported to cause a regression. There is a fix
    available, but I let it breed for a couple of days first.

    The irq departement provides:

    - new infrastructure to support non PCI based MSI interrupts
    - a couple of new irq chip drivers
    - the usual pile of fixlets and updates to irq chip drivers
    - preparatory changes for removal of the irq argument from interrupt
    flow handlers
    - preparatory changes to remove IRQF_VALID"

    * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (129 commits)
    irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sources
    irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2
    irqchip: Add documentation for the bcm2836 interrupt controller
    irqchip/bcm2835: Add support for being used as a second level controller
    irqchip/bcm2835: Refactor handle_IRQ() calls out of MAKE_HWIRQ
    PCI: xilinx: Fix typo in function name
    irqchip/gic: Ensure gic_cpu_if_up/down() programs correct GIC instance
    irqchip/gic: Only allow the primary GIC to set the CPU map
    PCI/MSI: pci-xgene-msi: Consolidate chained IRQ handler install/remove
    unicore32/irq: Prepare puv3_gpio_handler for irq argument removal
    tile/pci_gx: Prepare trio_handle_level_irq for irq argument removal
    m68k/irq: Prepare irq handlers for irq argument removal
    C6X/megamode-pic: Prepare megamod_irq_cascade for irq argument removal
    blackfin: Prepare irq handlers for irq argument removal
    arc/irq: Prepare idu_cascade_isr for irq argument removal
    sparc/irq: Use access helper irq_data_get_affinity_mask()
    sparc/irq: Use helper irq_data_get_irq_handler_data()
    parisc/irq: Use access helper irq_data_get_affinity_mask()
    mn10300/irq: Use access helper irq_data_get_affinity_mask()
    irqchip/i8259: Prepare i8259_irq_dispatch for irq argument removal

    Linus Torvalds

06 Aug, 2015

3 commits

  • IRQ_DOMAIN is a hidden config option, so depending on it doesn't
    make any sense. Select the config option because it's required to
    compile this driver.

    Signed-off-by: Stephen Boyd
    Reviewed-by: Andy Gross
    Signed-off-by: Greg Kroah-Hartman

    Stephen Boyd
  • Reviewed-by: Andy Gross
    Signed-off-by: Courtney Cavin
    Signed-off-by: Bjorn Andersson
    Tested-by: Tim Bird
    Signed-off-by: Greg Kroah-Hartman

    Courtney Cavin
  • Add tracepoints to retrieve information about read, write
    and non-data commands. For performance measurement support
    tracepoints are added at the beginning and at the end of
    transfers. Following is a list showing the new tracepoint
    events. The "cmd" parameter here represents the opcode, SID,
    and full 16-bit address.

    spmi_write_begin: cmd and data buffer.
    spmi_write_end : cmd and return value.
    spmi_read_begin : cmd.
    spmi_read_end : cmd, return value and data buffer.
    spmi_cmd : cmd.

    The reason that cmd appears at both the beginning and at
    the end event is that SPMI drivers can request commands
    concurrently. cmd helps in matching the corresponding

    SPMI tracepoints can be enabled like:

    echo 1 >/sys/kernel/debug/tracing/events/spmi/enable

    and will dump messages that can be viewed in
    /sys/kernel/debug/tracing/trace that look like:

    ... spmi_read_begin: opc=56 sid=00 addr=0x0000
    ... spmi_read_end: opc=56 sid=00 addr=0x0000 ret=0 len=02 buf=0x[01-40]
    ... spmi_write_begin: opc=48 sid=00 addr=0x0000 len=3 buf=0x[ff-ff-ff]

    Suggested-by: Sagar Dharia
    Acked-by: Steven Rostedt
    Reviewed-by: Stephen Boyd
    Signed-off-by: Gilad Avidov
    Signed-off-by: Ankit Gupta
    Signed-off-by: Greg Kroah-Hartman

    Ankit Gupta

29 Jul, 2015

2 commits

  • Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
    already have a pointer to corresponding irq_desc.

    Signed-off-by: Jiang Liu
    Cc: Greg Kroah-Hartman
    Link: http://lkml.kernel.org/r/20150713151750.915477120@linutronix.de
    Signed-off-by: Thomas Gleixner
    Signed-off-by: Ingo Molnar

    Jiang Liu
  • Chained irq handlers usually set up handler data as well. We now have
    a function to set both under irq_desc->lock. Replace the two calls
    with one.

    Search and conversion was done with coccinelle.

    Reported-by: Russell King
    Signed-off-by: Thomas Gleixner
    Cc: Greg Kroah-Hartman
    Cc: Jiang Liu
    Cc: Julia Lawall
    Link: http://lkml.kernel.org/r/20150713151750.831790045@linutronix.de
    Signed-off-by: Thomas Gleixner
    Signed-off-by: Ingo Molnar

    Thomas Gleixner

25 May, 2015

1 commit

  • Not all architectures have io memory.

    drivers/built-in.o: In function `spmi_pmic_arb_probe':
    spmi-pmic-arb.c:(.text+0x1ed399): undefined reference to `devm_ioremap_resource'

    Signed-off-by: Richard Weinberger
    Signed-off-by: Greg Kroah-Hartman

    Richard Weinberger

03 Apr, 2015

1 commit

  • Qualcomm PMIC arbiter driver already depends on ARCH_QCOM,
    which could be either ARM or ARM64. New version of the PMIC
    arbiter controller is available on 64 bit platforms.
    Remove ARM dependency to allow driver to be build for 64 bit

    Signed-off-by: Ivan T. Ivanov
    Signed-off-by: Greg Kroah-Hartman

    Ivan T. Ivanov

27 Mar, 2015

2 commits

  • Qualcomm PMIC Arbiter version-2 changes from version-1 are:

    - Some different register offsets.
    - New channel register space, one per PMIC peripheral (ppid).
    All tx traffic uses these channels.
    - New observer register space. All rx trafic uses this space.
    - Different command format for spmi command registers.

    Reviewed-by: Sagar Dharia
    Signed-off-by: Gilad Avidov
    Tested-by: Ivan T. Ivanov
    Signed-off-by: Greg Kroah-Hartman

    Gilad Avidov
  • According to spmi spec a slave powers up into startup state and then
    transitions into active state. Thus, the wakeup command is not required
    before calling the slave's probe. The wakeup command is only needed for
    slaves that are in sleep state after receiving the sleep command.

    Cc: galak@codeaurora.org
    Reviewed-by: Stephen Boyd
    Reviewed-by: Sagar Dharia
    Acked-by: Josh Cartwright
    Signed-off-by: Gilad Avidov
    Tested-by: Ivan T. Ivanov
    Signed-off-by: Greg Kroah-Hartman

    Gilad Avidov

20 Oct, 2014

1 commit

11 Jul, 2014

1 commit

09 Mar, 2014

2 commits

  • SPMI defines the behavior of a device in the "SLEEP" state as being
    "user-defined or specified by the device manufacturer". Without
    clearly-defined bus-level semantics for low-power states, push the
    responsibility of transitioning a device into/out of "SLEEP" into SPMI
    device drivers.

    Cc: Felipe Balbi
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Josh Cartwright
  • With the split of Qualcomm MSM support into legacy and multiplatform,
    the SPMI PMIC arb driver is only relevant on the multiplatform supported
    SoCs. Switch the Kconfig depends to ARCH_QCOM.

    Acked-by: Kumar Gala
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Josh Cartwright

16 Feb, 2014

3 commits

  • The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller,
    also implements interrupt handling for slave devices. Note, this is
    outside the scope of SPMI, as SPMI leaves interrupt handling completely

    Extend the driver to provide a irq_chip implementation and chained irq
    handling which allows for these interrupts to be used.

    Cc: Thomas Gleixner
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Josh Cartwright
  • Qualcomm's PMIC Arbiter SPMI controller functions as a bus master and
    is used to communication with one or more PMIC (slave) devices on the
    SPMI bus. The PMIC Arbiter is actually a hardware wrapper around the
    SPMI controller that provides concurrent and autonomous PMIC access
    to various entities that need to communicate with the PMIC.

    The SPMI controller hardware handles all of the SPMI bus activity (bus
    arbitration, sequence start condition, transmission of frames, etc).
    This software driver uses the PMIC Arbiter register interface to
    initiate command sequences on the SPMI bus. The status register is
    read to determine when the command sequence has completed and whether
    or not it completed successfully.

    Signed-off-by: Kenneth Heitke
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Kenneth Heitke
  • System Power Management Interface (SPMI) is a specification
    developed by the MIPI (Mobile Industry Process Interface) Alliance
    optimized for the real time control of Power Management ICs (PMIC).

    SPMI is a two-wire serial interface that supports up to 4 master
    devices and up to 16 logical slaves.

    The framework supports message APIs, multiple busses (1 controller
    per bus) and multiple clients/slave devices per controller.

    Signed-off-by: Kenneth Heitke
    Signed-off-by: Michael Bohan
    Signed-off-by: Josh Cartwright
    Signed-off-by: Greg Kroah-Hartman

    Kenneth Heitke